7733 datasheet(84/940 Pages) RENESAS

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7733 Group User's Manual

4–5

INTERRUPTS

Table 4.2.2 lists occurrence conditions of internal interrupt requests, which occur because of internal operations.

4.2 Interrupt sources

Table 4.2.2 Occurrence conditions of internal interrupt requests

Interrupt

Zero division

interrupt

BRK instruction

interrupt

Watchdog timer

interrupt

Timer Ai interrupt

(i = 0 to 4)

Timer Bi interrupt

(i = 0 to 2)

UARTi reception

interrupt (i = 0,1)

UARTi transmission

interrupt (i = 0,1)

UART2

transmission

/reception interrupt

A-D conversion

interrupt

Occurrence conditions of interrupt requests

Occurs when divider is “0” in execution of DIV instruction (Division instruction).

(Refer to “7700 Family Software Manual.”)

Occurs when the BRK instruction is executed.

(Refer to “7700 Family Software Manual.”)

Occurs when the most significant bit of the watchdog timer becomes “0.”

(Refer to chapter “10 WATCHDOG TIMER.”)

Occurrence condition depends on Timer Ai’s operating modes.

(Refer to chapter “6 TIMER A.”)

Occurrence condition depends on Timer Bi’s operating modes.

(Refer to chapter “7 TIMER B.”)

Occurs at serial data reception.

(Refer to chapter “8 SERIAL I/O.”)

Occurs at serial data transmission.

(Refer to chapter “8 SERIAL I/O.”)

Occurs at serial data transmission/reception.

(Refer to chapter “8 SERIAL I/O.”)

Occurs when A-D conversion is completed.

(Refer to chapter “9 A-D CONVERTER.”)

For external interrupts, refer to section “4.10 External interrupts.” For the key input interrupt, refer to

chapter “5 KEY INPUT INTERRUPT FUNCTION.”

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