7733 datasheet(92/940 Pages) RENESAS

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7733 Group User's Manual

4–13

INTERRUPTS

(2) Interrupt priority level detection time

Op-code fetch cycle

Sampling pulse

(a) 7 cycles

(b) 4 cycles

Interrupt priority level

detection time

(Note)

Note: This pulse resides when “2 cycles of

” is selected.

0 0

0 1

1 0

1 1

Processor mode register 0 (address 5E 16)

Processor mode bits

Wait bit

Software reset bit

Must be fixed to “0.”

Clock

output selection bit

7 cycles of clock

[(a) shown below]

4 cycles of clock

[(b) shown below]

2 cycles of clock

[(c) shown below]

Interrupt priority detection time selection bits

Do not select.

(1) Interrupt priority detection time selection bits

b5, b4

4.6 Interrupt priority level detection time

When the interrupt priority level detection time has passed after sampling starts, an interrupt request is

accepted. The interrupt priority level detection time can be selected by software. Figure 4.6.1 shows the

interrupt priority level detection time. Usually, select “2 cycles of

φ” as the interrupt priority level detection

time.

4.6 Interrupt priority level detection time

Fig. 4.6.1 Interrupt priority level detection time

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