Green Coarse Offset

Red Coarse Offset

HSOUT Output Start

MISC Control 4

TVP70025I

Subaddress

1Fh

Default (10h)

7

6

5

4

3

2

1

0

Reserved

Green Coarse Offset [5:0]

Green Coarse Offset [5:0]: 6-bit coarse analog offset for Green channel (applied before ADC). 6-bit sign magnitude value.

Subaddress

20h

Default (10h)

7

6

5

4

3

2

1

0

Reserved

Red Coarse Offset [5:0]

Red Coarse Offset [5:0]: 6-bit coarse analog offset for Red channel (applied before ADC). 6-bit sign magnitude value.

Subaddress

21h

Default (0Dh)

7

6

5

4

3

2

1

0

HSOUT Start [7:0]

HSOUT Start [7:0]: Adjusts the leading edge of the HSYNC output relative to the leading edge of the HSYNC input in pixel or clock cycles.

Subaddress

22h

Default (08h)

7

6

5

4

3

2

1

0

SP Reset

Yadj_delay [2:0]

MAC_EN

Coast Dis

VS Select

VS Bypass

SP Reset: Active-high reset for Sync Processing block. This bit may be used to manually reset the sync separator, sync accumulator, activity

and polarity detectors, and line and pixels counters.

0 = Normal operation (default)

1 = Sync processing reset

Yadj_delay [2:0]: Adjusts the phase delay of the luma output relative to the chroma output. Used to compensate for the chroma delay

associated with the 4:4:4 to 4:2:2 chroma sample conversion.

0h = Minimum delay (default)

7h = Maximum delay

MAC_EN: Toggling of the MAC_EN bit was required for TVP7000 and TVP7001 Macrovision support. This is no longer required with the

TVP70025I.

0 = Macrovision stripper disabled.

1 = Macrovision stripper enabled (default)

NOTE: When the Macrovsion stripper is enabled, sync separation and ALC and Clamp pulse placement is affected by the

Macrovision Stripper Width setting. See Register 34h for details.

Coast Dis: Active-high internal coast signal disable for 5-wire PC graphics inputs. Has no effect when the external coast signal is selected.

See bit 5 of register 0Fh.

0 = Internal coast signal enabled (default)

1 = Internal coast signal disabled

VS Select: VSYNC select

0 = VSOUT is generated by the sync separator.

1 = VSOUT is generated by the half line accumulator. (default)

VS Bypass: VSYNC timing bypass

0 = Normal operation (default). VS is derived from the sync separator or half line accumulator based on VS select, and the

internal pixel/line counters. Register 35h can be used to adjust VSOUT alignment relative to HSOUT.

1 = Bypass VSYNC processing. VSOUT is derived directly from the sync separator. VSOUT delay varies with sync separator

threshold (register 11h). Register 35h has no effect.

Copyright © 2008, Texas Instruments Incorporated

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