TVP70025IPZP datasheet(21/55 Pages) TI

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Embedded Syncs

Output Range Limits

Power Management

TVP70025I

www.ti.com ...................................................................................................................................................................................................... SLES232 – JUNE 2008

Standard embedded syncs insert SAV and EAV codes into the data stream on the rising and falling edges of

AVID. These codes contain the V and F bits that also define vertical timing. Table 4 gives the format of the SAV

and EAV codes.

H = 1 always indicates EAV. H = 0 always indicates SAV. The alignment of V and F to the line and field counter

varies depending on the standard. The P bits are protection bits:

P3 = V xor H

P2 = F xor H

P1 = F xor V

P0 = F xor V xor H

Table 4. EAV and SAV Sequence

Y9 (MSB)

Preamble

Status

The insertion location of the SAV/EAV codes on a video line is programmable using the AVID start/stop pixel

values located at subaddresses 40h through 43h.

NOTE:

When enabled (bit 0 of subaddress 15h), embedded syncs are present in both the Y

and C outputs.

The TVP70025I provides selectable output range limits in I2C subaddress 15h:

00 = RGB coding range (Y, Cb, and Cr range from 0 to 1023) (default)

01 = Extended coding range (Y, Cb, and Cr range from 4 to 1019)

10 = ITU-R BT.601 coding range (Y ranges from 64 to 940, Cb and Cr range from 64 to 960)

11 = Reserved

NOTE:

RGB coding range not allowed with embedded syncs.

The TVP70025I supports both automatic and manual power-down modes. The automatic power-down mode can

be selected by setting bit 2 of subaddress 0Fh to logic 0.

In the automatic power-down mode, the TVP70025I powers down the ADCs, the ADC reference, and horizontal

PLL when activity is not detected on both the selected HSYNC input and the selected SOG input (VSYNC is no

longer used). The TVP70025I restores power whenever activity is detected on either the selected HSYNC input

or the selected SOG input.

The TVP70025I also can be placed in power-down mode via the active-high PWDN input (pin 70). When the

PWDN input is driven high, the TVP70025I powers down everything including the I2C interface, and the digital

outputs are not placed in a high-impedance mode.

The TVP70025I also can be placed in a power-down mode using bit 1 of register 0Fh.

Individual blocks of the TVP70025I can be independently powered down using register 2Bh.

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