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TVP70025IPZP 数据表(PDF) 13 Page - Texas Instruments

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部件名 TVP70025IPZP
功能描述  TRIPLE 10-BIT, 90-MSPS, VIDEO AND GRAPHICS DIGITIZER WITH HORIZONTAL PLL
PDF  55 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TVP70025IPZP 数据表(HTML) 13 Page - Texas Instruments

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Programmable Gain Control
Programmable Offset Control
TVP70025I
www.ti.com ...................................................................................................................................................................................................... SLES232 – JUNE 2008
The selection between bottom- and mid-level clamping is performed by I2C subaddress 10h (see Section
Sync-On-Green Threshold). The fine clamps also must be enabled via I2C register 2Ah for proper operation. The
internal clamping time can be adjusted using the I2C clamp start and width registers at subaddress 05h and 06h,
respectively (see Clamp Start and Clamp Width).
Table 1. Recommended Clamp Setting by Video Mode
SOG INPUT
GREEN ADC CHANNEL
RED ADC CHANNEL
BLUE ADC CHANNEL
VIDEO MODE
(Y/G)
(Y/G)
(Pr/R)
(Pb/B)
YPbPr Component
Coarse
Fine Bottom Level
Fine Mid Level
Fine Mid Level
PC Graphics
Coarse
Fine Bottom Level
Fine Bottom Level
Fine Bottom Level
SCART-RGB
Coarse
Fine Bottom Level
Fine Bottom Level
Fine Bottom Level
A single-pole low-pass filter with three selectable cutoff frequencies (0.5, 1.7, and 4.8 MHz) is implemented in the
feedback loop of the sync-tip clamp circuit.
The TVP70025I provides a 4-bit coarse analog gain control (before A/D conversion) and an 8-bit fine digital gain
control (after A/D conversion). The coarse analog gain and the fine digital gain are both independently
programmable for each ADC channel.
Coarse Gain Control
The 4-bit coarse analog gain control has a 4:1 linear gain control range defined by the following equation.
Coarse Gain = 0.5 + NCG/10, where 0 ≤ NCG ≤ 15
0.5
≤ Coarse Gain ≤ 2.0
Default: NCG = 7 (Coarse Gain = 1.2)
The 4-bit coarse gain control can scale a signal with a voltage-input compliance of 0.5 VPP to 2 VPP to a full-scale
10-bit A/D output code range. The minimum gain corresponds to a code 0h (2-VPP full-scale input, –6-dB gain)
while the maximum gain corresponds to code Fh (0.5-VPP full scale, +6-dB gain). The 4-bit coarse gain control is
independently controllable for each ADC channel (Red Coarse Gain, Green Coarse Gain, and Blue Coarse
Gain).
Fine Gain Control
The 8-bit fine digital gain control has a 2:1 linear gain control range defined by the following equation.
Fine Gain = 1.0 + NFG/256 where 0 ≤ NFG ≤ 255
1.0
≤ Fine Gain < 2.0
Default: NFG = 0 (Fine Gain = 1.0)
The 8-bit fine gain control is independently controllable for each ADC channel (Red Fine Gain, Green Fine Gain,
and Blue Fine Gain). For a normal PC graphics input, the fine gain is used mostly.
The TVP70025I provides a 6-bit coarse analog offset control (before A/D conversion) and a 10-bit fine digital
offset control (after A/D conversion). The coarse analog offset and the fine digital offset are both independently
programmable for each ADC channel.
Coarse Offset Control
A 6-bit code sets the coarse offset (Red Coarse Offset, Green Coarse Offset, Blue Coarse Offset) with individual
adjustment per channel. The coarse offset ranges from –32 counts to +31 counts. The coarse offset registers
apply before the ADC.
Fine Offset Control
A 10-bit fine offset registers (Red Fine Offset, Green Fine Offset, Blue Fine Offset) apply after the ADC. The fine
offset ranges from –512 counts to +511 counts.
Copyright © 2008, Texas Instruments Incorporated
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Product Folder Link(s): TVP70025I



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