TDA9110 datasheet(18/29 Pages) STMICROELECTRONICS

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20k

Ω

220nF

From

Phase

Comparator

NOR1

6.5V

H-Lock CAP

3 HLOCKOUT

Figure 12 : LOCK/UNLOCK Block Diagram

OPERATING DESCRIPTION (continued)

The TDA9110 also includes a Lock/Unlock identifi-

cation block which senses in real time whether the

the PLL1 is locked or not on the incominghorizontal

synchro signal. The resulting information is avail-

able on Hlockout (see Synchro Processor). The

block function is described in Figure 12.

The NOR1 gate receive the phase comparator

output pulses (which also drive the charge pump).

When the PLL1 is locked, we have on point A a very

small negative pulse (about 100ns) at each hori-

zontal cycle, so after the RC filter, there is a high

level on Pin 14 which forces Hlockout to high level.

The hysterisis comparator detects locking when

Pin 14 reachs 6.5V and unlocking when Pin 14

decreases to 6.0V.

When the PLL1 is unlocked, the 100ns negative

pulse on Abecomes much larger and consequently

the average level on Pin 14 decreases. It forces

Hlockout to low level.

The Pin 14 status is approximately the following :

- near 0V when there is no H-Sync

- between 0 and 4V with H-Sync frequency differ-

ent from VCO

- between 4 to 8 V when VCO frequency reaches

H-Sync one (but not already in phase)

- near 8V when PLL1 is locked.

It is important to notice that Pin 14 is not an

output pin but is only used for filtering purpose

(see Figure 12).

The lock/unlock information is also available

through the I

2C read.

II.3 - PLL2

The PLL2 ensures a constant position of the

shaped flyback signal in comparison with the saw-

tooth of the VCO (Figure 13).

The phase comparator of PLL2 (phase type com-

parator) is followed by a charge pump (typical

output current : 0.5mA).

The flyback input consists of an NPN transistor.

This input must be current driven. The maximum

H Osc

Sawtooth

H Drive

1.6V

3.7V

6.4V

7/8T

1/8T

Duty Cycle

Internally

Shaped Flyback

Flyback

The duty cycle of H-drive is adjustable between 30% and 60%.

Figure 13 : PLL2 Timing Diagram

20k

Ω

GND 0V

HFLY

400

Ω

Figure 14 : Flyback Input Electrical Diagram

recommanded input current is 5mA (see Fig-

ure 14).

The duty cycle is adjustable through I

2C from 30%

to 60%. For Start Up safe operation, the initial duty

cycle (afterPower on reset) is 60% in order to avoid

to have a too long conduction of the BU transistor.

Themaximumstoragetime is about38% (TFLY/2.TH).

Typically, TFLY/TH is around 20% which means that

Ts max is around 28%.

TDA9110

18/29

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