TDA9110 datasheet(23/29 Pages) STMICROELECTRONICS

23 / 29 page

Typical maximum and minimum frequency, at 25

and without any correction (S correction or C cor-

rection), can be calculated by :

f(Max.) = 2.5 x f0 and f(Min.) = 0.33 x f0

If S or C corrections are applied, these values are

slighty affected.

If a synchronization pulse is applied, the internal

oscillator is automaticaly caught but the amplitude

is no more constant. An internal correction is acti-

vated to adjust it in less than a half a second : the

highest voltage of the ramp Pin 22 is sampled on

the sampling capacitor connected on Pin 20 at

each clock pulse and a transconductanceamplifier

generates the charge current of the capacitor. The

ramp amplitude becomes again constant.

The read status register enables to have the verti-

cal Lock-Unlock and the vertical Synchro Polarity

informations.

We recommand to use a AGC capacitor with low

leakage current. A value lower than 100nA is man-

datory.

A good stability of the internal closed loop is

reached by a 470nF

± 5% capacitor value on

Pin 20 (VAGC).

III.6 - I

2C Control Adjustments

Then, S and C correction shapes can be added to

this ramp. These frequence independent S and C

corrections are generated internally. Their ampli-

tudes are adjustable by their respective I

2C regis-

ter. They can also be inhibited by their Select bit.

Finally, the amplitude of this S and C corrected

ramp can be adjusted by the vertical ramp ampli-

tude control register.

The adjusted ramp is available on Pin 23 (VOUT)to

drive an external power stage.

The gain of this stage is typically 25% depending

on its register value.

The DC value of this ramp is driven by its own I

r egi s t er ( ver ti c a l P osi t i on) . I ts v a lue is

VCDOUT = 7/16

⋅ VREF ± 300mV.

The VDCOUT voltage is correlated with DC value of

VOUT. It increases the accuracy when temperature

varies.

By using the vertical moire, VDCOUT can be modu-

lated from frame to frame. This function is intended

to correct slightly the vertical video line to line

period from actual CRT line to line width.

III.7 - Basic Equations

In first approximation, the amplitude of the ramp on

Pin 23 (Vout) is :

VOUT -VMID =(VOSC -VMID)

⋅ (1 + 0.25 (VAMP))

with VMID = 7/16

⋅ VREF ; typically 3.5V, the middle

value of the ramp on Pin 22

VOSC =V22 , ramp with fixed amplitude

VAMP is -1 for minimum vertical amplitude register

value and +1 for maximum

On VDCOUT, the voltage (in volts) is calculated by :

VDCOUT =VMID + 0.3 (VPOS)

with VPOS equals -1 for minimum vertical position

The current available on Pin 22 is :

IOSC =

⋅ VREF⋅ COSC ⋅ f

with COSC : capacitor connected on Pin 22

f : synchronization frequency

OPERATING DESCRIPTION (continued)

TDA9110

23/29

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