TDA9112 datasheet(28/51 Pages) STMICROELECTRONICS

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TDA9112

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Figure 2. Horizontal sync signal

9.2.2 - Sync. presence detection flags

The sync. signal presence detection flags in the

status register (VDet, HVDet, VExtrDet) do not

show in real time the presence or absence of cor-

responding sync. signal. They are latched to 1 as

soon as a single sync. pulse is detected. In order

to reset them to 0 (all at once), a 1 must be written

into SDetReset I2C bus bit, the reset action taking

effect with ACK bit of the I2C bus transfer to the

circuits are ready to capture another event (pulse).

See Note 53.

Figure 3. Extraction of V-sync signal from H/V-sync signal

9.2.3 - MCU controlled sync. selection mode

I2C bus bit VSyncAuto is set to 0. The MCU reads

the polarity and signal presence detection flags,

after setting the SDetReset bit to 1 and an appro-

priate delay, to obtain a true information of the sig-

nals applied, reads and evaluates this information

and controls the vertical signal selector according-

ly. The MCU has no access to polarity inverters,

they are controlled automatically.

See also chapter I2C BUS CONTROL REGISTER

MAP.

9.2.4 - Automatic sync. selection mode

I2C bus bit VSyncAuto is set to 1. In this mode, the

device itself controls the I

2C bus bits switching the

polarity inverters (HVPol, VPol) and the vertical

sync. signal selector (VSyncSel), using the infor-

mation provided by the detection circuitry. If both

extracted and pure vertical sync. signals are

present, the one already selected is maintained.

No intervention of the MCU is necessary.

9.3 - HORIZONTAL SECTION

9.3.1 - General

The horizontal section consists of two PLLs with

various adjustments and corrections, working on

horizontal deflection frequency, then phase shift-

ing and output driving circuitry providing H-drive

signal on HOut pin. Input signal to the horizontal

section is output of the polarity inverter on H/

HVSyn input. The device ensures automatically

that this polarity be always positive.

9.3.2 - PLL1

The PLL1 block diagram is in Figure 5. It consists

of a voltage-controlled oscillator (VCO), a shaper

with adjustable threshold, a charge pump with inhi-

bition circuit, a frequency and phase comparator

and timing circuitry. The goal of the PLL1 is to

make the VCO ramp signal match in frequency the

sync. signal and to lock this ramp in phase to the

sync. signal. On the screen, this offset results in

the change of horizontal position of the picture.

The loop, by tuning the VCO accordingly, gets and

maintains in coincidence the rising edge of input

sync. signal with signal REF1, deriving from the

VCO ramp by a comparator with threshold adjust-

able through

HPOS I2C bus control. The coinci-

dence is identified and flagged by lock detection

circuit on pin HLckVBk as well as by HLock I2C

bus flag.

The charge pump provides positive and negative

currents charging the external loop filter on HPosF

pin. The loop is independent of the trailing edge of

sync. signal and only locks to its leading edge. By

design, the PLL1 does not suffer from any dead

band even while locked. The speed of the PLL1

Positive

Negative

tPulseHSyn

H/V-sync

Integration

Extracted

textrV

tPulseHsyn

V-sync

Internal

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