TDA9112 datasheet(38/51 Pages) STMICROELECTRONICS

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TDA9112

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the voltage on pin BISense exceeds the internal

threshold VThrBIsCurr. This represents current limi-

tation if a voltage proportional to the current

through the power component or deflection stage

is available on pin BISense. This threshold is af-

fected by voltage on pin HPosF, which rises at soft

start and descends at soft stop. This ensures self-

contained soft control of duty cycle of the output

signal on pin BOut. Refer to Figure 10. Another

condition for reset of the R-S flip-flop, OR-ed with

the one described before, is that the voltage on pin

BISense exceeds the voltage VC2, which depends

on the voltage applied on input BISense of the er-

ror amplifier O1. The two voltages are compared,

and the reset signal generated by the comparator

C2. The error amplifier amplifies (with a factor de-

fined by external components) the difference be-

tween the input voltage proportional to DC/DC

convertor output voltage and internal reference

VBReg. The internal reference and so the output

voltage is I2C bus adjustable by means of

BREF

I2C bus control.

Both step-up (DC/DC converter output voltage

higher than its input voltage) and step-down (out-

put voltage lower than input) are possible in this

configuration.

9.7.2 - Internal sawtooth configuration.

In internal sawtooth configuration, the voltage on

BISense pin is set higher than VThrBIsConf thresh-

old, switching the switches S1 and S2 to “int.” po-

sition. Internal sawtooth needed to generate the

horizontal parabola component on HVDyCor out-

put is used as reference for the comparison with

the regulated output voltage, and so for the timing

of the signal on BOut output. The R-S flip-flop is

set at the sawtooth discharge, which ends at the

beginning of a new sawtooth ramp. The high level

at the Q output of the R-S flip-flop only passes at

that moment thanks to invertor I1 and the NAND

gate. The Off-to-On edge at the output is thus syn-

chronized to the beginning of the HVDyCor output

horizontal parabola. This can be positioned to the

beginning or middle of the H-flyback pulse, see

paragraph Composite horizontal and vertical dy-

namic correction output HVDyCor on page 36.

Timing of the R-S flip-flop reset only depends on

the voltage VC1 from the error amplifier, which op-

erates in the same way like in external sawtooth

configuration, including reference voltage adjust-

ment. As no current limitation is carried out, only a

step-down operation is possible in this configura-

tion.

DC/DC controller Off-to-On edge timing

Config uration

BOutPh

(Sad07/D7)

BOHEdge

(Sad17/D3)

Timing of Off-to-O n transition on BOut

output

Internal sawtooth

don’t care

Start of H-parab. on HVDyCor

External sawtooth

don’t care

Middle of H-flyback plus tBTrigDel

External sawtooth

Falling edge of H-drive signal

External sawtooth

Rising edge of H-drive signal

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