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TDA9203 数据表(PDF) 8 Page - STMicroelectronics |
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TDA9203 数据表(HTML) 8 Page - STMicroelectronics |
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8 / 13 page ![]() t HDAT t SUDAT t LOW t HIGH t HDS t SUP t BUF SDA SCL Figure 7 I 2C INTERFACE TIMINGS REQUIREMENTS (see Figure 7) Symbol Parameter Min. Typ. Max. Unit tBUF Time the bus must be free between 2 access 1300 ns tHDS Hold Time for Start Condition 600 ns tSUP Set-up Time for Stop Condition 600 ns tLOW The Low Period of Clock 1300 ns tHIGH The High Period of Clock 600 ns tHDAT Hold Time Data 300 ns tSUDAT Set-up Time Data 250 ns tR,tF Rise and Fall Time of both SDA and SCL 20 300 ns TDA9203A 8/13 |
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