BLK

HSYNC

BPCP

Figure 1

FUNCTIONAL DESCRIPTION

Input Stage

The R, G and B signals must be fed to the three

inputs through coupling capacitors (100nF).

The maximum input peak-to-peak video amplitude

is 1V.

The input stage includes a clamping function. This

clamp is using the input serial capacitor as ”mem-

ory capacitor” and is gated by an internally gener-

ated ”Back-Porch-Clamping-Pulse (BPCP)”.

The synchronization edge of the BPCP is selected

according bit 0 of register R8.

When B0R8 is set to 1, the BPCP is synchronized

on the leading edge of the blankingpulse BLKinputs

on Pin14 (seeFigure1). B7R8 allows to use positive

or negative blanking signal on Pin 14. At power on

reset TDA9203A use only positive blanking.

When B0R8 is clear to 0, the BPCP is synchronized

on the second edge of the horizontal pulse HSYNC

inputs on Pin 24. An automatic function allows to

use positive or negative horizontal pulse on Pin 24

(see Figure 2).

In both case BPCP width is adjustable by I

and B2 of register R8 (see R8 Table P8).

Contrast Adjustment (8 bits)

The contrast adjustment is made by controlling

simultaneously the gain of three internal variable

gain amplifiers through the I

The contrast adjustment allows to cover a typical

range of 48dB.

ABL Control

The TDA9203A I

input (automatic beam limitation) to attenuat e

R,G,B video signals according to beam intensity.

The operating range is 2.5V typicaly, from 5.3V to

2.8V. A typical 12dB Max. attenuation is applied to

the signal whatever the current gain is. Refer to

Figure 3 for ABL input attenuation range.

In case of software control, the ABL input must be

consumption (see Figure 11).

resistor is 10k

Ω and equivalent schematic given in

Figure 11.

HSYNC

BPCP

Figure 2

Brightness Adjustment (8 bits)

As for the contrast adjustment, the brightness is

controlled by I

The brightness function consists to add the same

DC offset to the three R, G, B signals after contrast

amplification. This DC-Offset is present only out-

side the blanking pulse (see Figure 4).

The DC output level during the blanking pulse, is

Drive Adjustment (3 x 8 bits)

In order to adjust the white balance , the TDA9203A

offers the possibility to adjust separately the overall

gain of each complete video channel. The gain of

each channel is controlled by I

The very large drive adjustment range (48dB) allows

different standard or custom color temperature.

It can also be used to adjust the output voltages at

the optimum amplitude to drive the C.R.T drivers,

keepingthe whole contrast control for end-useronly.

The drive adjustment is located after the CON-

TRAST, BRIGHTNESS and OSD switch blocks, so

that the white balance will remains correct when

BRT is adjusted, and will also be correct on OSD

portion of the signal.

2

0

-2

-4

-6

-8

-10

-12

-14

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Attenuation (dB)

V

Figure 3

TDA9203A

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