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PSD4235G2 数据表(PDF) 73 Page - STMicroelectronics

部件名 PSD4235G2
功能描述  Flash In-System-Programmable Peripherals for 16-Bit MCUs
PDF  93 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

PSD4235G2 数据表(HTML) 73 Page - STMicroelectronics

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PSD4000 Series
Preliminary Information
70
-70
-90
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
tLVLX
ALE or AS Pulse Width
15
20
tAVLX
Address Setup Time
(Note 1)
4
6
ns
tLXAX
Address Hold Time
(Note 1)
7
8
ns
tAVWL
Address Valid to Leading
Edge of WR
(Notes 1 and 3)
8
15
ns
t SLWL
CS Valid to Leading Edge of WR
(Note 3)
12
15
ns
t DVWH
WR Data Setup Time
(Note 3)
25
35
ns
t WHDX
WR Data Hold Time
(Note 3)
4
5
ns
t WLWH
WR Pulse Width
(Note 3)
28
35
ns
tWHAX1
Trailing Edge of WR to Address
Invalid
(Note 3)
6
8
ns
tWHAX2
Trailing Edge of WR to DPLD
Address Input Invalid
(Note 3 and 4)
0
0
ns
tWHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
27
30
ns
tAVPV
Address Input Valid to Address
(Note 2)
20
25
ns
Output Delay
Write Timing (5 V ± 10% Versions)
NOTES: 1.
Any input used to select an internal PSD4000 function.
2.
In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
3.
WR timing has the same timing as E, DS, LDS, UDS, WRL, and WRH signals.
4.
tWHAX2 is Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.
Microcontroller Interface – PSD4000 AC/DC Parameters
(5V ± 10% Versions)
-70
-90
Slew
TURBO
Rate
Symbol
Parameter
Conditions
Min
Max
Min
Max
OFF
(Note 1)
Unit
tPD
PLD Input Pin/Feedback to
20
25
Add 12
Sub 2
ns
PLD Combinatorial Output
tARD
PLD Array Delay
11
16
ns
PLD Combinatorial Timing (5 V ± 10%)
NOTE: 1. Fast Slew Rate output available on Port C and F.



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