PSD4235G2 datasheet(56/93 Pages) STMICROELECTRONICS

56 / 93 page

Preliminary Information

PSD4000 Series

The

PSD4000

Functional

Blocks

(cont.)

9.4.6 Port D – Functionality and Structure

Port D has four I/O pins. See Figure 22. Port D can be configured to program one or more

of the following functions:

t MCU I/O Mode

t PLD Input – direct input to PLD

Port D pins can be configured in PSDsoft as input pins for other dedicated functions:

t PD0 – ALE, as address strobe input

t PD1 – CLKIN, as clock input to the PLD and APD counter

t PD2 – CSI, as active low chip select input. A high input will disable the

Flash/SRAM and CSIOP.

t PD3 – WRH, as active low Write Enable (high byte) input or as DBE input from

68HC912

9.4.7 Port E – Functionality and Structure

Port E can be configured to perform one or more of the following functions (see Figure 23):

t MCU I/O Mode

t In-System Programming – JTAG port can be enabled for programming/erase of the

PSD4000 device. (See Section 9.6 for more information on JTAG programming.)

Pins that are configured as JTAG pins in PSDsoft will not be available for other I/O

functions.

t Open Drain – Port E pins can be configured in Open Drain Mode

t Battery Backup features – PE6 can be configured as a Battery Input (Vstby) pin.

PE7 can be configured as a Battery On Indicator output

pin, indicating when Vcc is less than Vbat.

t Latched Address Output – Provided latched address (A7-0) output

DATA OUT

REG.

READ MUX

PLD INPUT

DIR REG.

DATA IN

OUTPUT

SELECT

OUTPUT

MUX

PORT D PIN

DATA OUT

Figure 22. Port D Structure

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