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AD5667BCPZ-R2 数据表(PDF) 6 Page - Analog Devices

部件名 AD5667BCPZ-R2
功能描述  Dual, 12-/14-/16-Bit nanoDACs짰 with 5 ppm/째C On-Chip Reference, I2C짰 Interface
PDF  32 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD5667BCPZ-R2 数据表(HTML) 6 Page - Analog Devices

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AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 6 of 32
I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted.1
Table 4.
Parameter
Conditions2
Min
Max
Unit
Description
fSCL3
Standard mode
100
kHz
Serial clock frequency
Fast mode
400
kHz
High speed mode, CB = 100 pF
3.4
MHz
High speed mode, CB = 400 pF
1.7
MHz
t1
Standard mode
4
μs
tHIGH, SCL high time
Fast mode
0.6
μs
High speed mode, CB = 100 pF
60
ns
High speed mode, CB = 400 pF
120
ns
t2
Standard mode
4.7
μs
tLOW, SCL low time
Fast mode
1.3
μs
High speed mode, CB = 100 pF
160
ns
High speed mode, CB = 400 pF
320
ns
t3
Standard mode
250
ns
tSU;DAT, data setup time
Fast mode
100
ns
High speed mode
10
ns
t4
Standard mode
0
3.45
μs
tHD;DAT, data hold time
Fast mode
0
0.9
μs
High speed mode, CB = 100 pF
0
70
ns
High speed mode, CB = 400 pF
0
150
ns
t5
Standard mode
4.7
μs
tSU;STA, setup time for a repeated start condition
Fast mode
0.6
μs
High speed mode
160
ns
t6
Standard mode
4
μs
tHD;STA, hold time (repeated) start condition
Fast mode
0.6
μs
High speed mode
160
ns
t7
Standard mode
4.7
μs
tBUF, bus free time between a stop and a start condition
Fast mode
1.3
μs
t8
Standard mode
4
μs
tSU;STO, setup time for a stop condition
Fast mode
0.6
μs
High speed mode
160
ns
t9
Standard mode
1000
ns
tRDA, rise time of SDA signal
Fast mode
300
ns
High speed mode, CB = 100 pF
10
80
ns
High speed mode, CB = 400 pF
20
160
ns
t10
Standard mode
300
ns
tFDA, fall time of SDA signal
Fast mode
300
ns
High speed mode, CB = 100 pF
10
80
ns
High speed mode, CB = 400 pF
20
160
ns
t11
Standard mode
1000
ns
tRCL, rise time of SCL signal
Fast mode
300
ns
High speed mode, CB = 100 pF
10
40
ns
High speed mode, CB = 400 pF
20
80
ns
t11A
Standard mode
1000
ns
tRCL1, rise time of SCL signal after a repeated start condition and after
an acknowledge bit
Fast mode
300
ns
High speed mode, CB = 100 pF
10
80
ns
High speed mode, CB = 400 pF
20
160
ns



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