AD5667BCPZ-R2 datasheet(21/32 Pages) AD

21 / 32 page

AD5627R/AD5647R/AD5667R, AD5627/AD5667

Rev. 0 | Page 21 of 32

SERIAL INTERFACE

The AD56x7R/AD56x7 have 2-wire I2C-compatible serial

interfaces (refer to I2C-Bus Specification, Version 2.1, January 2000,

available from Philips Semiconductor). The AD56x7R/AD56x7

can be connected to an I2C bus as a slave device, under the control

of a master device. See Figure 3 for a timing diagram of a

typical write sequence.

The AD56x7R/AD56x7 support standard (100 kHz), fast

(400 kHz), and high speed (3.4 MHz) data transfer modes.

High speed operation is only available on select models. See

the Ordering Guide for a full list of models. Support is not

provided for 10-bit addressing and general call addressing.

The AD56x7R/AD56x7 each have a 7-bit slave address. The five

MSBs are 00011 and the two LSBs (A1, A0) are set by the state

of the ADDR address pin. The facility to make hardwired

changes to ADDR allows the user to incorporate up to three of

these devices on one bus, as outlined in Table 7.

Table 7. Device Address Selection

ADDR Pin Connection

VDD

No Connection

GND

The 2-wire serial bus protocol operates as follows:

The master initiates data transfer by establishing a start

condition when a high-to-low transition on the SDA line

occurs while SCL is high. The following byte is the address

byte, which consists of the 7-bit slave address. The slave

address corresponding to the transmitted address responds

by pulling SDA low during the 9th clock pulse (this is

termed the acknowledge bit). At this stage, all other devices

on the bus remain idle while the selected device waits for

data to be written to, or read from, its shift register.

Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge

bit). The transitions on the SDA line must occur during the

low period of SCL and remain stable during the high

period of SCL.

When all data bits have been read or written, a stop

condition is established. In write mode, the master pulls

the SDA line high during the 10th clock pulse to establish a

stop condition. In read mode, the master issues a no

acknowledge for the 9th clock pulse (that is, the SDA line

remains high). The master then brings the SDA line low

before the 10th clock pulse, and then high during the 10th

clock pulse to establish a stop condition.

WRITE OPERATION

When writing to the AD56x7R/AD56x7, the user must begin

with a start command followed by an address byte (R/W= 0),

after which the DAC acknowledges that it is prepared to receive

data by pulling SDA low. The AD56x7R/AD56x7 requires two

bytes of data for the DAC and a command byte that controls

various DAC functions. Three bytes of data must therefore be

written to the DAC, the command byte followed by the most

significant data byte and the least significant data byte, as

shown in Figure 54. All these data bytes are acknowledged by

the AD56x7R/AD56x7. A stop condition follows.

READ OPERATION

When reading data back from the AD56x7R/AD56x7, the user

begins with a start command followed by an address byte

(R/W = 1), after which the DAC acknowledges that it is

prepared to transmit data by pulling SDA low. Three bytes of

data are then read from the DAC, which are acknowledged by

the master, as shown in Figure 55. A stop condition follows.

HIGH SPEED MODE

The AD5627RBRMZ and the AD5667RBRMZ offer high speed

serial communication with a clock frequency of 3.4 MHz. See

the Ordering Guide for details.

High speed mode communication commences after the master

addresses all devices connected to the bus with the Master Code

00001XXX to indicate that a high speed mode transfer is to

begin (see Figure 56). No device connected to the bus is

permitted to acknowledge the high speed master code.

Therefore, the code is followed by a no acknowledge. The

master must then issue a repeated start followed by the device

address. The selected device then acknowledges its address.

All devices continue to operate in high speed mode until the

master issues a stop condition. When the stop condition is

issued, the devices return to standard/fast mode. The part also

returns to standard/fast mode when CLR is activated while the

part is in high speed mode.

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