TMX320C6747ZKB3 datasheet(4/203 Pages) TI

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1.3 Description

TMS320C6745/6747 Floating-point Digital Signal Processor

SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008

www.ti.com

The C6745/6747 is a Low-power digital signal processor based on C674x DSP core. It provides

significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The C6745/6747 enables OEMs and ODMs to quickly bring to market devices featuring high processing

performance .

The C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P)

is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache.

The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program

and data space. L2 also has a 1024KB ROM. L2 memory can be configured as mapped memory, cache,

or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional

128KB RAM shared memory ( C6747 only) is available for use by other hosts without affecting DSP

performance.

The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output

(MDIO) module; two inter-integrated circuit (I2C) Bus interfaces; 3 multichannel audio serial port (McASP)

with 16/9 serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one

configurable as watchdog); a configurable 16-bit host port interface (HPI) [C6747 only]; up to 8 banks of

16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes,

multiplexed with other peripherals; 3 UART interfaces (one with RTS and CTS); 3 enhanced

high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module

peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM)

outputs; 2 32-bit enhanced quadrature pulse (eQEP) peripherals; and 2 external memory interfaces: an

asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a

higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6745/6747

and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and

100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO)

interface is available for PHY configuration.

The rich peripheral set provides the ability to control external peripheral devices and communicate with

external processors. For details on each of the peripherals, see the related sections later in this document

and the associated peripheral reference guides.

TMS320C6745/6747 Floating-point Digital Signal Processor

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