TMX320C6747ZKB3 datasheet(8/203 Pages) TI

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Device Overview

3.1 Device Characteristics

TMS320C6745/6747 Floating-point Digital Signal Processor

SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008

www.ti.com

Table 3-1 provides an overview of the C6745/6747 Low power digital signal processor. The table shows

significant features of the device, including the capacity of on-chip RAM, peripherals, and the package

type with pin count.

Table 3-1. Characteristics of the C6745/C6747 Processor

HARDWARE FEATURES

C6745

C6747

EMIFB

SDRAM only, 16-bit bus width

SDRAM only, 16/32-bit bus width

Asynchronous (8-bit bus width) RAM,

Asynchronous (8/16-bit bus width) RAM,

EMIFA

Flash, NOR, NAND

Flash, 16-bit SDRAM, NOR, NAND

Flash Card Interface

MMC and SD cards supported.

EDMA3

32 independent channels, 8 QDMA channels, 2 Transfer controllers

2 64-Bit General Purpose (configurable as 2 separate 32-bit timers, 1 configurable as

Timers

Watch Dog)

UART

3 (one with RTS and CTS flow control)

SPI

2 (Each with one hardware chip select)

I2C

2 (both Master/Slave)

Multichannel Audio

2 (each with transmit/receive, FIFO buffer,

3 (each with transmit/receive, FIFO buffer,

Serial Port [McASP]

16/9 serializers)

Peripherals

10/100 Ethernet MAC

Not all peripherals pins

with Management Data

1 (RMII Interface)

are available at the

I/O

same time (for more

eHRPWM

6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs

detail, see the Device

Configurations section). eCAP

3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs

eQEP

2 32-bit QEP channels with 4 inputs/channel

UHPI

1 (16-bit multiplexed address/data)

Full Speed Host Or Device with On-Chip

High-Speed OTG Controller with on-chip

USB 2.0 (USB0)

PHY

OTG PHY

Full-Speed OHCI (as host) with on-chip

USB 1.1 (USB1)

PHY

General-Purpose

8 banks of 16-bit

Input/Output Port

LCD Controller

1 (32 KHz oscillator and seperate power

RTC

trail. Provides time and date tracking and

alarm capability.)

Size (Bytes)

488KB RAM, 1088KB ROM

DSP

32KB L1 Program (L1P)/Cache (up to 32KB)

32KB L1 Data (L1D)/Cache (up to 32KB)

On-Chip Memory

256KB Unified Mapped RAM/Cache (L2)

Organization

1024KB ROM (L2)

DSP Memories can be made accessible to EDMA3, and other peripherals.

ADDITIONAL SHARED MEMORY

128KB RAM

C674x CPU ID + CPU

Control Status Register

0x1400

Rev ID

(CSR.[31:16])

C674x Megamodule

Revision ID Register

0x0000

Revision

(MM_REVID[15:0])

JTAG BSDL_ID

JTAGID Register

0x0B7D_F02F

CPU Frequency

MHz

674x DSP 300 MHz

Cycle Time

674x DSP 3.33 ns

Device Overview

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