MPC8640D datasheet(33/140 Pages) FREESCALE

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

Figure 12 shows the GMII receive AC timing diagram.

Figure 12. GMII Receive AC Timing Diagram

8.2.3

MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

8.2.3.1

MII Transmit AC Timing Specifications

Table 29 provides the MII transmit AC timing specifications.

Figure 13 shows the MII transmit AC timing diagram.

Table 29. MII Transmit AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

TX_CLK clock period 10 Mbps

tMTX

—

400

—

TX_CLK clock period 100 Mbps

tMTX

—40

—

TX_CLK duty cycle

tMTXH/tMTX

—

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

tMTKHDX

TX_CLK data clock rise time (20%-80%)

tMTXR

1.0

—

4.0

TX_CLK data clock fall time (80%-20%)

tMTXF

1.0

—

4.0

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII

transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in

general, the clock reference symbol representation is based on two to three letters representing the clock of a particular

functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

RX_CLK

RXD[7:0]

tGRDXKH

tGRX

tGRXH

tGRXR

tGRXF

tGRDVKH

RX_DV

RX_ER

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