MPC8640D datasheet(49/140 Pages) FREESCALE

部件名	MPC8640D

功能描述	Integrated Host Processor Hardware Specifications

PDF	140 Pages

Scroll/Zoom	100%

制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Local Bus

Figure 27. Local Bus Signals (PLL Bypass Mode)

NOTE

In PLL bypass mode, LCLK[n] is the inverted version of the internal clock

with the delay of tLBKHKT. In this mode, signals are launched at the rising edge

of the internal clock and are captured at falling edge of the internal clock,

with the exception of the LGTA/LUPWAIT signal, which is captured at the

rising edge of the internal clock.

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

tLBKLOV2

LCLK[n]

Input Signals:

LAD[0:31]/LDP[0:3]

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

LALE

tLBIXKH1

Input Signal:

LGTA

Output (Address) Signal:

LAD[0:31]

tLBIVKH1

tLBIXKL2

tLBIVKL2

tLBKLOX1

tLBKLOZ2

tLBOTOT

Internal launch/capture clock

tLBKLOX2

tLBKLOV1

tLBKLOV3

tLBKLOZ1

tLBKHKT

tLBKLOV4

LUPWAIT

MPC8640D 数据表(PDF) 49 Page - Freescale Semiconductor, Inc

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