LPC2102 datasheet(13/32 Pages) NXP

13 / 32 page

LPC2101_02_03_3

Product data sheet

Rev. 03 — 7 October 2008

13 of 32

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

6.7 Fast general purpose parallel I/O

Device pins that are not connected to a speciﬁc peripheral function are controlled by the

GPIO registers. Pins may be dynamically conﬁgured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back, as well as the current state of the port pins.

LPC2101/02/03 introduce accelerated GPIO functions over prior LPC2000 devices:

• GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing.

• Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

• All GPIO registers are byte addressable.

• Entire port value can be written in one instruction.

6.7.1 Features

• Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

• Direction control of individual bits.

• Separate control of output set and clear.

• All I/O default to inputs after reset.

6.8 10-bit ADC

The LPC2101/02/03 contain one ADC. It is a single 10-bit successive approximation ADC

with eight channels.

6.8.1 Features

• Measurement range of 0 V to 3.3 V.

• Each converter capable of performing more than 400,000 10-bit samples per second.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition on input pin or Timer Match signal.

• Every analog input has a dedicated result register to reduce interrupt overhead.

6.9 UARTs

The LPC2101/02/03 each contain two UARTs. In addition to standard transmit and

receive data lines, UART1 also provides a full modem control handshake interface.

Compared to previous LPC2000 microcontrollers, UARTs in LPC2101/02/03 include a

fractional baud rate generator for both UARTs. Standard baud rates such as 115200 can

be achieved with any crystal frequency above 2 MHz.

6.9.1 Features

• 16 byte Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes

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