LPC2101_02_03_3

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 — 7 October 2008

15 of 32

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

6.12 SSP serial I/O controller

The LPC2101/02/03 each contain one SSP. The SSP controller is capable of operation on

a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the

bus. However, only a single master and a single slave can communicate on the bus during

a given data transfer. The SSP supports full duplex transfers, with data frames of 4 bits to

16 bits flowing from the master to the slave and from the slave to the master. Often only

one of these data streams carries meaningful data.

6.12.1 Features

Semiconductor’s Microwire buses

6.13 General purpose 32-bit timers/external event counters

The Timer/Counter is designed to count cycles of the Peripheral Clock (PCLK) or an

externally supplied clock and optionally generate interrupts or perform other actions at

specified timer values, based on four match registers. It also includes four capture inputs

to trap the timer value when an input signal transitions, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

The LPC2101/02/03 can count external events on one of the capture inputs if the

minimum external pulse is equal or longer than a period of the PCLK. In this configuration,

unused capture lines can be selected as regular timer capture inputs or used as external

interrupts.

6.13.1 Features

value when an input signal transitions. A capture event may also optionally generate

an interrupt.

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

following capabilities:

– Set LOW on match.