LPC2292 datasheet(13/53 Pages) NXP

13 / 53 page

LPC2292_2294_7

Product data sheet

Rev. 7 — 4 December 2008

13 of 53

NXP Semiconductors

LPC2292/LPC2294

16/32-bit ARM microcontrollers with external memory interface

P3[17]/A17

48[7]

N5[7]

A17 — External memory address line 17.

P3[18]/A18

47[7]

M5[7]

A18 — External memory address line 18.

P3[19]/A19

46[7]

L5[7]

A19 — External memory address line 19.

P3[20]/A20

45[7]

K5[7]

A20 — External memory address line 20.

P3[21]/A21

44[7]

N4[7]

A21 — External memory address line 21.

P3[22]/A22

41[7]

K4[7]

A22 — External memory address line 22.

P3[23]/A23/

XCLK

40[7]

N3[7]

I/O

A23 — External memory address line 23.

XCLK — Clock output.

P3[24]/CS3

36[7]

M2[7]

CS3 — LOW-active Chip Select 3 signal.

(Bank 3 addresses range 0x8300 0000 to 0x83FF FFFF)

P3[25]/CS2

35[7]

M1[7]

CS2 — LOW-active Chip Select 2 signal.

(Bank 2 addresses range 0x8200 0000 to 0x82FF FFFF)

P3[26]/CS1

30[7]

K2[7]

CS1 — LOW-active Chip Select 1 signal.

(Bank 1 addresses range 0x8100 0000 to 0x81FF FFFF)

P3[27]/WE

29[7]

K1[7]

WE — LOW-active Write enable signal.

P3[28]/BLS3/

AIN7

28[6]

J4[6]

BLS3 — LOW-active Byte Lane Select signal (Bank 3).

AIN7 — ADC, input 7. This analog input is always connected

to its pin.

P3[29]/BLS2/

AIN6

27[6]

J3[6]

BLS2 — LOW-active Byte Lane Select signal (Bank 2).

AIN6 — ADC, input 6. This analog input is always connected

to its pin.

P3[30]/BLS1

97[7]

E13[7]

BLS1 — LOW-active Byte Lane Select signal (Bank 1).

P3[31]/BLS0

96[7]

F10[7]

BLS0 — LOW-active Byte Lane Select signal (Bank 0).

TD1

22[7]

H2[7]

TD1: CAN1 transmitter output.

RESET

135[8]

C5[8]

External Reset input: A LOW on this pin resets the device,

causing I/O ports and peripherals to take on their default

states, and processor execution to begin at address 0. TTL

with hysteresis, 5 V tolerant.

XTAL1

142[9]

C3[9]

Input to the oscillator circuit and internal clock generator

circuits.

XTAL2

141[9]

B3[9]

Output from the oscillator ampliﬁer.

VSS

3, 9, 26, 38,

54, 67, 79,

93, 103, 107,

111, 128

C2, E4, J2,

N2, N7, L10,

K12, F13,

D11, B13,

B11, D7

Ground: 0 V reference.

VSSA

139

Analog ground: 0 V reference. This should nominally be the

same voltage as VSS, but should be isolated to minimize noise

and error.

VSSA(PLL)

138

PLL analog ground: 0 V reference. This should nominally be

the same voltage as VSS, but should be isolated to minimize

noise and error.

VDD(1V8)

37, 110

N1, A12

1.8 V core power supply: This is the power supply voltage

for internal circuitry.

Table 4.

Pin description …continued

Symbol

Pin (LQFP)

(TFBGA)[1]

Type

Description

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