P89LPC954 datasheet(49/69 Pages) NXP

49 / 69 page

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

49 of 69

NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

8.4.6 Single step mode

This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any

combination of the eight input channels can be selected for conversion. After each

channel is converted, an interrupt is generated, if enabled, and the ADC waits for the next

start condition. May be used with any of the start modes.

8.5 Conversion start modes

8.5.1 Timer triggered start

An A/D conversion is started by the overﬂow of Timer 0. Once a conversion has started,

additional Timer 0 triggers are ignored until the conversion has completed. The Timer

triggered start mode is available in all ADC operating modes.

8.5.2 Start immediately

Programming this mode immediately starts a conversion. This start mode is available in all

ADC operating modes.

8.5.3 Edge triggered

An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has

started, additional edge triggers are ignored until the conversion has completed. The edge

triggered start mode is available in all ADC operating modes.

8.6 Boundary limits interrupt

The ADC has both a high and low boundary limit register. The user may select whether an

interrupt is generated when the conversion result is within (or equal to) the high and low

boundary limits or when the conversion result is outside the boundary limits. An interrupt

will be generated, if enabled, if the result meets the selected interrupt criteria. The

boundary limit may be disabled by clearing the boundary limit interrupt enable.

An early detection mechanism exists when the interrupt criteria has been selected to be

outside the boundary limits. In this case, after the four MSBs have been converted, these

four bits are compared with the four MSBs of the boundary high and low registers. If the

four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits)

an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt

criteria, the boundary limits will again be compared after all 8 MSBs have been converted.

A boundary status register (BNDSTA0) ﬂags the channels which caused a boundary

interrupt.

8.7 Clock divider

The ADC requires that its internal clock source be in the range of 320 kHz to 9 MHz to

maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is

provided for this purpose.

8.8 Power-down and Idle mode

In Idle mode the ADC, if enabled, will continue to function and can cause the device to exit

Idle mode when the conversion is completed if the A/D interrupt is enabled. In

Power-down mode or Total Power-down mode, the ADC does not function. If the ADC is

enabled, it will consume power. Power can be reduced by disabling the ADC.

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