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CS5532-AS 数据表(PDF) 44 Page - Cirrus Logic

部件名 CS5532-AS
功能描述  16-bit and 24-bit ADCs with Ultra-low-noise PGIA
PDF  50 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS5532-AS 数据表(HTML) 44 Page - Cirrus Logic

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CS5531/32/33/34-AS
44
DS289F5
3. PIN DESCRIPTIONS
Clock Generator
OSC1; OSC2 - Master Clock.
An inverting amplifier inside the chip is connected between these pins and can be used with a
crystal to provide the master clock for the device. Alternatively, an external (CMOS compatible)
clock (powered relative to VD+) can be supplied into the OSC2 pin to provide the master clock
for the device.
Control Pins and Serial Data I/O
CS - Chip Select.
When active low, the port will recognize SCLK. When high the SDO pin will output a high
impedance state. CS should be changed when SCLK = 0.
1
2
3
4
5
6
7
817
18
19
20
21
22
23
24
9
10
11
12
13
14
15
16
CS5533/4
VREF+
VREF-
CS
DGND
SDO
SERIAL DATA INPUT
POSITIVE ANALOG POWER
AMPLIFIER CAPACITOR CONNECT
AMPLIFIER CAPACITOR CONNECT
DIFFERENTIAL ANALOG INPUT
CHIP SELECT
VOLTAGE REFERENCE INPUT
VOLTAGE REFERENCE INPUT
DIFFERENTIAL ANALOG INPUT
DIFFERENTIAL ANALOG INPUT
POSITIVE DIGITAL POWER
DIGITAL GROUND
SERIAL DATA OUT
MASTER CLOCK
DIFFERENTIAL ANALOG INPUT
AIN3+
AIN3-
SDI
VD+
NEGATIVE ANALOG POWER
DIFFERENTIAL ANALOG INPUT
DIFFERENTIAL ANALOG INPUT
DIFFERENTIAL ANALOG INPUT
DIFFERENTIAL ANALOG INPUT
AIN2-
AIN2+
A1
A0
VA-
VA+
C2
C1
AIN4-
AIN4+
OSC1
OSC2
AIN1-
AIN1+
SCLK
SERIAL CLOCK INPUT
LOGIC OUTPUT (ANALOG)/GUARD
LOGIC OUTPUT (ANALOG)
MASTER CLOCK
1
2
3
4
5
6
7
813
14
15
16
17
18
19
20
VREF+
VREF-
SCLK
CS
DGND
A1
A0
VA-
VA+
C2
C1
AIN1-
AIN1+
9
10
11
12
SDO
OSC1
OSC2
SERIAL DATA INPUT
LOGIC OUTPUT (ANALOG)/GUARD
POSITIVE ANALOG POWER
AMPLIFIER CAPACITOR CONNECT
AMPLIFIER CAPACITOR CONNECT
DIFFERENTIAL ANALOG INPUT
CHIP SELECT
VOLTAGE REFERENCE INPUT
VOLTAGE REFERENCE INPUT
DIFFERENTIAL ANALOG INPUT
DIFFERENTIAL ANALOG INPUT
SERIAL CLOCK INPUT
POSITIVE DIGITAL POWER
DIGITAL GROUND
SERIAL DATA OUT
MASTER CLOCK
CS5531/2
DIFFERENTIAL ANALOG INPUT
AIN2+
AIN2-
SDI
VD+
NEGATIVE ANALOG POWER
MASTER CLOCK
LOGIC OUTPUT (ANALOG)



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