LPC2921 datasheet(13/81 Pages) PHILIPS

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LPC2921_2923_2925_0

Preliminary data sheet

Rev. 00.01 — 24 October 2008

13 of 81

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN and LIN

6.6.3.1

ETM/ETB

The ETM provides real-time trace capability for deeply embedded processor cores. It

outputs information about processor execution to a trace buffer. A software debugger

allows configuration of the ETM using a JTAG interface and displays the trace information

that has been captured in a format that a user can easily understand. The ETB stores

trace data produced by the ETM.

The ETM/ETB module has the following features:

• Closely tracks the instructions that the ARM core is executing.

• On-chip trace data storage (ETB).

• All registers are programmed through JTAG interface.

• Does not consume power when trace is not being used.

• THUMB/Java instruction set support.

6.6.4 Power supply pins

Table 6 shows the power supply pins.

6.7 Clocking strategy

6.7.1 Clock architecture

The LPC2921/2923/2925 contains several different internal clock areas. Peripherals like

Timers, SPI, UART, CAN and LIN have their own individual clock sources called base

clocks. All base clocks are generated by the Clock Generator Unit (CGU0). They may be

unrelated in frequency and phase and can have different clock sources within the CGU.

The system clock for the CPU and AHB Bus infrastructure has its own base clock. This

means most peripherals are clocked independently from the system clock. See Figure 4

for an overview of the clock areas within the device.

Within each clock area there may be multiple branch clocks, which offers very flexible

control for power-management purposes. All branch clocks are outputs of the Power

Management Unit (PMU) and can be controlled independently. Branch clocks derived

from the same base clock are synchronous in frequency and phase. See Section 6.15 for

more details of clock and power control within the device.

Two of the base clocks generated by the CGU0 are used as input into a second,

dedicated CGU (CGU1). The CGU1 uses its own PLL and fractional dividers to generate

the base clock for the USB controller and one base clock for an independent clock output.

Table 6.

Power supply pins

Symbol

Description

VDD(CORE)

digital core supply 1.8 V

VSS(CORE)

digital core ground (digital core, ADC1/2)

VDD(IO)

I/O pins supply 3.3 V

VSS(IO)

I/O pins ground

VDD(OSC_PLL)

oscillator and PLL supply

VSS(OSC_PLL)

oscillator and PLL ground

VDDA(ADC3V3)

ADC1 and ADC2 3.3 V supply

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