March 1996

This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without no tice.

PLCC68

8

I0-I7

BUSY

OFL

12

O0-O1 1

2

OC0-OC1

DS

PRESET

VSS

VDD

W.A.R. P.

2.0

LASTIN

MCLK

WAIT

ENDOFL

ERR

OE

AUTO

3

SIS0-SIS2

RD

READY

Figure 1. Logic Diagram.

Digital Fuzzy Co-processor 8-bit I/O

High Speed Rules Processing

4 Input, 2 Output, 32 Rules in 33.1

µs

Up to 256 Rules (4 Antecedents,1 Consequent)

Up to 8 Input Configurable Variables

Up to 16 Membership Functions for an Input

Variable

Antecedent Membership Functions with

Triangular and Trapezoidal Shape

Up to 4 Output Variables

Up to 256 Membership Functions for all

Consequents

Singleton Consequent Membership Functions

Defuzzification on chip

Maximum Clock Frequency 40MHz

A/D Start Convertion Pulse presettable

Direct Interface to all popular microprocessor

Handshaking Signal Polarity presettable

Operates ”STAND ALONE” (without

µP) if

desired

Standard +5V Supply Voltage

Software Tools and Emulators Availability

Pin number: 52

68-lead Plastic Leaded Chip Carrier package.

ANTECE DENT

MEMORY

P ROGRAM &

CONSE QUENT

MEMORY

P ROGRAMMABLEA/D

OUTPUT PULSE

INTERNAL BUS

Input Port

with

HANDSHAKE

8

ALPHA

CALCULATOR

INFE RENCE

UNIT

DEFUZZIFIER

Ouput Port

with

HANDSHAKE

8

Figure 2. Simplified Block Diagram.

W.A.R.P.2.0

8-BIT FUZZY CO-PROCESSOR

PRELIMINARY DATA

1/28