3-39

TELCOM SEMICONDUCTOR, INC.

7

6

5

4

3

1

2

8

TC520A

TC520A-1 9/16/96

B

LOAD

CMPTR

CMPTR

DV

DGND

CE

VDD

A

DIN

OSCOUT

DCLK

OSCIN

DOUT

READ

1

14

213

312

411

510

69

78

TC520ACPD

8

1

14

2

13

3

12

4

11

5

10

6

9

7

TC520ACOE

DIN

B

15

16

LOAD

DV

DGND

CE

VDD

DCLK

A

DOUT

OSCOUT

READ

OSCIN

N/C

N/C

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

LOGIC

CONTROL

GATE

8-BIT COUNTER

÷256

8-BIT SHIFT REG.

÷4

GATE

7

SYSCLK

8

6

A

B

CMPTR

CE

DV

5

4

3

14

13

GATE

TIME OUT

FORCE AUTO-ZERO

POLARITY BIT

CLEAR COUNT

1

2

VDD

GND

16-BIT COUNTER

18-BIT SHIFT REGISTER

GATE

OVERRANGE

BIT

11

12

9

10

8

READ

DCLK

DOUT

LOAD

DIN

16

OSCIN

OSCOUT

Pin Out of

14-Pin Package

SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY

FEATURES

s

Converts TC500/500A/510/514 to Serial Operation

s

Programmable Conversion Rate and Resolution

for Maximum Flexibility

s

Supports up to 17 Bits of Accuracy Plus

Polarity Bit

s

Low Power Operation: Typically 7.5mW

s

14-Pin DIP or 16-Pin SOIC Packages

s

Polled or Interrupt Mode Operation

ORDERING INFORMATION

Operating

Part No.

Package

Temp. Range

TC520ACOE

16-Pin SOIC (Wide)

0

°C to +70°C

TC520ACPD

14-Pin Plastic DIP

0

°C to +70°C

TC500EV

Evaluation Kit for TC500 Family

EVALUATION

KIT

AVAILABLE

GENERAL DESCRIPTION

The TC520A Serial Interface Adapter provides logic

control for TelCom's TC500/500A/510/514 family of dual

slope, integrating A/D converters. It directly manages TC500

converter phase control signals A, B, and CMPTR thereby

reducing host processor task loading and software complex-

ity. Communication with the TC520A is accomplished over

a 3 wire serial port. Key converter operating parameters are

programmable for complete user flexibility.

Data conversion initiated when the CE input is brought

low. The converted data (plus overrange and polarity bits)

are held in an 18 bit shift register until read by the processor,

or until the next conversion is completed. Data may be

clocked out of the TC520A at any time, and at any rate the

user prefers. A Data Valid (DV) output is driven active at the

start of each conversion cycle indicating the 18 bit shift

register update has just been completed. This signal may be

polled by the processor, or can be used as data ready

interrupt.

The TC520A timebase can be derived from an external

frequency source of up to 6MHz; or can operate from its own

external crystal. It requires a single 5V logic supply and

dissipates less than 7.5mW.