3-41

TELCOM SEMICONDUCTOR, INC.

7

6

5

4

3

1

2

8

TC520A

SERIAL INTERFACE ADAPTER FOR

TC500 A/D CONVERTER FAMILY

Pin No.

Pin No.

14-Pin PDIP 16-Pin SOIC

Package

Package

Symbol

Description

11

Input. +5V

±10% power supply input with respect to DGND.

2

2

DGND

Input. Digital Ground.

3

3

CMPTR

Input, active high or low (depending on polarity of the voltage input to A/D

converter). This pin connects directly to the zero-crossing comparator output

(CMPTR) of the TC5xx A/D converter. A High-to-Low state change on this pin

causes the TC520A to terminate the de-integrate phase of conversion.

4

4

B

Output, active high. The A and B outputs of the TC520A connect directly to the

A and B inputs of the TC5xx A/D converter connected to the TC520A. The

binary code on A, B determines the conversion phase of the TC5xx A/D

converter: (A, B) = 01 places the TC5xx A/D converter into the Auto Zero

phase; (A, B) =10 for Integrate phase (INT); (A, B) =11 for De-integrate phase

family data sheets for a complete description of these phases of operation.

5

5

A

Output, active high. See pin 4 description above.

6

6

Input. This pin connects to one side of an AT-cut crystal having a effective

series resistance of 100

Ω (typ) and a parallel capacitance of 20pF (typ). If an

external frequency source is used to clock the TC520A, this pin must be left

floating.

7

7

Input. This pin connects to the other side of the crystal described in pin 6

above. The TC520A may also be clocked from an external frequency source

connected to this pin. The external frequency source must be a pulse train

having a duty cycle of 30% (minimum); rise and fall times of 15nsec and a min/

be left floating. A maximum operating frequency of 4MHz (crystal) or 6MHz

(external clock source) is permitted.

8

N/C

No connection on 16 pin package version.

9

N/C

No connection on 16 pin package version.

8

10

READ

Input, active low, level and negative edge triggered. A high-to low transition on

READ loads serial port output shift register with the most recent converted

data. Data is loaded such that the first bit transmitted from the TC520A to the

processor is the overrange bit (OVR), followed by the polarity bit (POL) (high =

input positive; low = input negative). This is followed by a 16 bit data word

a high impedance state. A serial port read access cycle is terminated at any

time by bringing READ high.

911

Output, logic level. Serial port output pin. This pin is enabled only when READ

is low (see READ pin description).

10

12

Input, positive and negative edge triggered. Serial port clock. With READ low,

PIN DESCRIPTIONS

DETAILED DESCRIPTION

The TC520A input and output signals are outlined in the

table below.