Software Compatible 6809 CPU

Memec Design

February 25, 2003

2

Optimized for

Core Deliverables

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Netlist Version

o

Netlist compatible with the Actel Designer place and route tool

•

RTL Version

o

VHDL Source Code

o

Test Bench

•

All

o

User Guide

Synthesis and Simulation Support

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Synthesis: Synplicity

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Simulation: ModelSim

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Other tools supported upon request

Verification

•

Test Bench

Figure 1: Logic Symbol

clk

irq_n

firq_n

nmi_n

seq_state

cc

pc

stack

reset_n

bus_busy

bus_rd_data

stack_operation

opcode

mem_rdy

rd_trf_ebl

wr_trf_ebl

bus_want

bus_rw_n

bus_wr_data

bus_addr

Bus Interface Unit

Bus Request Unit

6809