Software Compatible 6809 CPU

Memec Design

February 25, 2003

4

Optimized for

Condition Code (CC) Register

Beginning with bit(0) the condition code register contains following flags:

C:

Carry from ALU

V:

Overflow (2 complement) from ALU

Z:

Zero from ALU

N:

Negative (2 complement) from ALU

I:

Interrupt mask register for irq_n

H:

Half Carry (low nibble) from ALU

F:

Interrupt mask for firq_n

E:

Entire Flag for irq_n/firq_n stack operations

Direct Page (DP) Register

These registers enhance the direct addressing mode. During direct addressing instruction execution, the contents of

DP appears at the higher address outputs (A15- A8).

Instructions

The MC-ACT-6809 supports all 6809 instructions like load, store, and, or, add, sub, transfer/exchange instructions

for all registers, 8 by 8 unsigned multiply, decimal adjust and signed/unsigned conditional branches. A powerful

stack command is also available. Software interrupts are supported.

Addressing Modes

Nearly all instructions can be combined with the following addressing modes:

Inherent:

Register source and destination, no post bytes, e.g. INCA

Immediate:

Postbyte is parameter, e.g. LDA #100

Extended:

Postbytes are address, e.g. LDA 1000

Direct:

Postbyte is low address, DP is high address, e.g. LDA <50

Indexed:

Postbyte(s) define indexed mode:

- (Index registers are X,Y,U,S)

- Post incr. by 1 and 2, e.g. LDA ,S++

- Pre decr. by 1 and 2, e.g. LDA ,-X

- Zero offset, e.g. LDA 0,X

- signed offset, e.g. LDA -7,Y

- A/B/D signed offset, e.g. LDB A,U

- 8/16bit signed offset PC relative, e.g. LDA 665,PCR

Indexed indirect: The same types as indexed may be used. The indirect mode uses the argument of the index mode

as address for an indirect access.

Illegal Instructions

To insure save operation, illegal opcodes are recognized and will lead to an exception, where a vector is fetched to

enter the exception handler routine. For this purpose, the reserved vector of the 6809 is used. The address of the

illegal instruction is pushed on the S stack.