Software Compatible 6809 CPU

Memec Design

February 25, 2003

6

Optimized for

Device Requirements

Family

Device

Utilization

Performance

COMB

SEQ

Total

SX-A

SX32A-3

1625 (91%)

344 (32%)

1969 (69%)

28 MHz

ProASIC

PLUS

APA150-STD

n/a

n/a

2795 (46%)

11 MHz

Axcelerator

AX500-3

1577 (30%)

339 (13%)

1916 (24%)

31 MHz

Table 1: Device Utilization and Performance

Verification and Compliance

Functional and timing simulation has been performed on the 6809 using VHDL and Verilog Test Benches.

Simulation vectors used for verification are provided with the core. This core has also been used successfully in

customer designs.

Signal Descriptions

The following signal descriptions define the IO signals.

Signal

Direction

Description

clk

in

system clock, rising edge used only

reset_n

in

asynchronous system reset, active low, goes to all flip flops

nmi_n

in

Non maskable interrupt, active low

firq_n

in

Fast interrupt request, active low

irq_n

in

Interrupt request, active low

bus_busy

in

Bus busy, If ‘1’ the uP can not access the bus and waits until bus is released.

wr_trf_ebl

out

Write transfer enable

bus_want

out

Bus want. The uP requests the bus.

rd_trf_ebl

out

Read transfer enable

rw_n

out

Read / write-not. If ‘1’ then read cycle

bus_addr[15:0]

out

Bus address

bus_rd_data[7:0]

in

Read data

bus_wr_data[7:0]

out

Write data

mem_rdy

out

Memory ready, see ‘Internal Bus Interface Timing’ for timing diagram

seq_state[5:0]

out

Command sequencer state register

cc[7:0]

out

Condition code register

pc[15:0]

out

Program counter register

stack[15:0]

out

Stack pointer

stack_operation

out

Stack operation, if ‘1’ a stack operation cycle is running

opcode[5:0]

out

Operation code

Table 2: Core I/O Signals