LT3751EUFD datasheet(18/28 Pages) LINER

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LT3751

3751f

APPLICATIONS INFORMATION

RVOUT & RBG Selection

RVOUT should be selected based on VOUT comparator trip

current. RVOUT current should be designed between 100μA

and 4mA to maintain accuracy.

RVOUT =

VOUT,TRIP + VDIODE

⎛

⎝⎜

⎞

⎠⎟

+ VTRANS − 55V

400

μA

RBG sets the trip current and is directly related to the

selection of RVOUT.

RBG =

0.98 •RVOUT

VOUT,TRIP + VDIODE

⎛

⎝⎜

⎞

⎠⎟

− VTRANS

RVOUT

RVTRANS

− 1

⎛

⎝⎜

⎞

⎠⎟

NMOS Switch Selection

Choose an external NMOS power switch with minimal gate

charge and on-resistance that satisﬁes current limit and

voltage break-down requirements. The gate is nominally

driven to VCC – 2V during each charge cycle. Ensure that

this does not exceed the maximum gate to source voltage

rating of the NMOS but enhances the channel enough to

minimize the on-resistance.

Similarly, the maximum drain-source voltage rating of the

NMOS must exceed VTRANS + VOUT/N or the magnitude

of the leakage inductance spike, whichever is greater. The

maximum instantaneous drain current rating must exceed

selected current limit. Because the switching period de-

Table 2. Recommended NMOS Transistors

MANUFACTURER

PART NUMBER

ID (A)

VDS(MAX) (V)

RDS(ON) (mΩ)

QG(TOT) (nC)

PACKAGE

Fairchild Semiconductor

www.fairchildsemi.com

FDS2582

FQB19N20L

FQP34N20L

4.1

150

200

140

SO-8

TO-252

TO-220

On Semiconductor

www.onsemi.com

MTD6N15T4G

NTD12N10T4G

NTB30N20T4G

NTB52N10T4G

150

100

200

100

300

165

DPAK

D2PAK

Vishay

www.vishay.com

Si7820DN

Si7818DN

SUP33N20-60P

2.6

3.4

200

150

200

240

135

12.1

1212-8

TO-252

creases with output voltage, the average current though

the NMOS is greatest when the output is nearly charged

and is given by:

IAVG,M =

IPK •VOUT(PK)

2(VOUT(PK) +N• VTRANS)

See Table 2 for recommended external NMOS transistors.

Gate Driver Operation

The LT3751 gate driver has an internal, selectable 10.5V

or 5.6V clamp with up to 2A current capability (using

LVGATE). For 10.5V operation, tie CLAMP pin to ground,

and for 5.6V operation, tie the CLAMP pin to the VCC pin.

Choose a clamp voltage that does not exceed the NMOS

manufacturer’s maximum VGS ratings. The 5.6V clamp

can also be used to reduce LT3751 power dissipation

and increase efﬁciency when using logic-level FETs. The

typical gate driver overshoot voltage is 0.5V above the

clamp voltage.

The LT3751’s gate driver also incorporates a PMOS pull-up

device via the LVGATE pin. The PMOS pull-up driver should

only be used for VCC applications of 8V or below. Operating

LVGATE with VCC above 8V will cause permanent damage

to the part. LVGATE is active when tied to HVGATE and

allows rail-to-rail gate driver operation. This is especially

useful for low VCC applications, allowing better NMOS

drive capability. It also provides the fastest rise times,

given the larger 2A current capability verses 1.5A when

using only HVGATE.

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