LT3751EUFD datasheet(20/28 Pages) LINER

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LT3751

3751f

APPLICATIONS INFORMATION

Care should also be taken in placement of the sense lines.

The negative return line, CSN, must be a dedicated trace

to the low side resistor terminal. Haphazardly routing the

CSN connection to the ground plane can cause inaccurate

current limit.

Under/Overvoltage Lockout

The LT3751 provides user-programmable under and

overvoltage lockouts for both VCC and VTRANS. Use the

equations in the Pin Functions section for proper selection

of resistor values. When under/overvoltage lockout com-

parators are tripped, the master latch is disabled, power

delivery is halted, and the FAULT pin goes low. Adequate

supply bulk capacitors should be used to reduce power

supply voltage ripple that could cause false tripping during

normal switching operation.

The LT3751 provides internal zener clamping diodes to

protect itself in shutdown when VTRANS is operated above

55V. Supply voltages should only be applied to UVLO1,

UVLO2, OVLO1 and OVLO2 with series resistance such

that the Absolute Maximum pin currents are not exceeded.

Pin current can be calculated using:

IPIN =

VAPPLIED − 55V

RSERIES

Note that in shutdown, RVTRANS, RVOUT, RDCM, UVLO1,

UVLO2, OVLO1 and OVLO2 currents increase signiﬁcantly

when operating VTRANS above the zener clamp voltages

and are inversely proportional to the external series pin

resistances.

NMOS Snubber Design

The transformer leakage inductance causes a parasitic

voltage spike on the drain of the power NMOS switch dur-

ing the turn-off transition. Transformer leakage inductance

effects become more apparent at high peak primary cur-

rents. The worst-case magnitude of the voltage spike is

determined by the energy stored in the leakage inductance

and the total capacitance on the VDRAIN node.

VD,LEAK =

LLEAK •I

CVDRAIN

Two problems can arise from large VD,LEAK. First, the

magnitude of the spike may require an NMOS with an

unnecessarily high V(BR)DSS which equates to a larger

RDS(ON). Secondly, the VDRAIN node will ring—possibly

below ground—causing false tripping of the DCM com-

parator or damage to the NMOS switch (see Figure 12).

Both issues can be remedied using a snubber. If leakage

inductance causes issues, it is recommended to use a RC

snubber in parallel with the primary winding, as shown

in Figure 11. Size CSNUB and RSNUB based on the desired

leakage spike voltage, known leakage inductance, and an

RC time constant less than 1μs. Otherwise, the leakage

voltage spike can cause false tripping of the VOUT com-

parator and stop charging prematurely.

Figure 11. RC Snubber Circuit

3751 F11

LPRI

RSNUB

CSNUB

LLEAK

•

CVDRAIN

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