General Description

Each channel performs serial-to-parallel conversion on data characters received from a peripheral device, and parallel-to serial conversion on data characters re-

ceived from the CPU. The CPU can read the complete status of each channel at any time. Reported status information includes the type and condition of the transfer

operations being performed, as well as any error conditions (parity, overrun, framing, or break interrupt). Synchronization for the serial data stream is accomplished

by adding start and stops bits to the transmit data to form a data character (character orientated protocol). An optional parity bit can be attached to the data character

to enhance data integrity. The receiver checks the parity bit for any transmission bit errors. The channels of the Multichannel UART (UARTM) are designed to reduce

CPU overhead when working with highspeed modems and other devices, because the core can buffer several bytes and burst them to the CPU instead of generating

a costly interrupt cycle on every byte. Therefore, the interrupt overhead can be amortized over several bytes, thus increasing performance. The core was designed

to be compact by time-slicing a single UART engine instead of instantiating multiple instances. The time-slicing technique allows for the core to be smaller and more

space efficient. Each channel has its own baud rate generator, interrupt controller and prioritizer, receive and transmit FIFOs, and CPU registers. The user has control

over the configuration of the core by modifying the parameters in the top-level source file. This allows the core to be modified and reused easily. These parameters

include number of channels and FIFO depth. The core comes with a testbench to aid the customer with integration and verification.

Figure 1: MC-ACT-UARTM Logic Symbol

Functional Description

The 16550 UARTM is includes a time-division multiplexed (time-sliced) version of the MC-ACT-UART core. The microprocessor interface is similar to the standard

16550 UART interface with the possible inclusion of up to 4 additional address bits to select up to 16 channels. Integration of the core into existing designs that are

replacing an array of discrete chips is easy since each channel is mapped to the standard 16550 register set using the lower three address bits.

TIME-SLICED ARCHITECTURE

The core is time multiplexed across NUM_CHANNELS serial input lines, where NUM_CHANNELS is the number of channels and is either 4, 8 or 16. It is set by the

user when instantiating the core. This means that instead of duplicating the core logic NUM_CHANNELS times, the logic is shared between all channels. This also

means that the logic must retain the state of each channel after each time slice is finished. The state machine and sampling register values of a given channel are

stored in memory or in registers so that they can be reloaded when the time multiplexing returns to the channel NUM_CHANNELS time slices later. This technique

reduces the size of the core.

The time slice period is a function of three constants – the highest baud rate in the system, 16 samples per serial bit, and the number of channels in the system,

NUM_CHANNELS. The time slice period determines what the system clock should be. For example, a system clock of 29.4912 MHz is needed for a 16-channel

system with all channels running at the maximum baud rate of 115,200 bps. (115,200 bps x 16 samples per bit x 16 channels = 29.4912 MHz).

A[m:0]

data_in[7:0]

CS_N

INTR

CPU

Interface

MODEM

and

Status

Interface

SIN[N]

SOUT[N]

CLK

RD_N

WR_N

RESET_N

Note: N = Number of UART Channels

ADS_N

dout_enable

data_out[7:0]

OUT2_N[N]

OUT1_N[N]

DTR_N[N]

RTS_N[N]

CTS_N[N]

DSR_N[N]

DCD_N[N]

RI_N[N]

rst_2_gbuf

earlyRst_2_gbuf

rst

from rst_2_gbuf

earlyRst

from earlyRst_2_gbuf