UART_BAUD

The UART_BAUD block provides each channel with a divide-by-N clock enable based on the CLK input, where N is the 16-bit value of that channel’s Divisor Latch

Register (DLR). This sampling rate represents a frequency that is 16x the desired baud rate for the channel. This oversampling allows the Transmitter and Receiver

Control blocks to properly detect start and stop bits, and to utilize samples during the middle of the bit transmission period to guarantee proper framing of data.

Like the Transmitter and Receiver Control blocks, the UART_BAUD is time multiplexed across the NUM_CHANNELS channels. The logic is shared between all

channels in the same manner as with the other blocks. The state of the UART_BAUD block is stored in memory for each time slice so that it can be restored when

the time multiplexing returns to the channel NUM_CHANNELS time slices later.

The UART_BAUD block uses a counter to delay the toggling of the clock enable by the appropriate number of CLK cycles, as determined by the Divisor Latch Regis-

ter for that channel. If the user modifies the contents of the Divisor Latch Register, the new value will be loaded into the counter on the next successive time slice and

the clock enable signal will reflect the new sampling frequency.

With an input clock to the Core of 1.8423 MHz times the number of Channels, the recommended Divisor Latch settings are provided below for common baud rates.

Table 2: Divisor Latch values for a Core clock of NUM_CHANNELS * 1.8423 MHz

FIFO

The FIFO module is comprised of the RX_FIFO, the TX_FIFO, and the FIFO_CTRL modules.

RX_FIFO

The Receiver FIFO module consists of NUM_CHANNELS independent configurable depth FIFOs. Each FIFO is 11-bits wide to support 8-bit characters plus LSR[4:2]

for that symbol.

When the correct number of bytes have been stored in the FIFO as set by bits 6 and 7 of the FIFO control register (FCR), the Data Ready bit is set for that channel

in the Line Status Register, LSR[0] and an interrupt is sent to the microprocessor which fetches the byte from the receive holding register (RHR) for the channel that

caused the interrupt. Parity, framing, and overrun errors are detected and their corresponding bits are set in the line status register (LSR).

TX_FIFO

The Transmitter FIFO module consists of NUM_CHANNELS independent configurable depth FIFOs. Each FIFO is 8-bits wide to support 8-bit characters.

HOST_REGISTERS

This block implements the bulk of the functionality of the 16550 host interface for all channels. It also contains all the host accessible registers for the design. This

block manages the Interrupt priority and subsequent Interrupt generation for all channels.

HOST_INTF

This block provides support for an asynchronous microprocessor interface, which is used to read and write the register set, and load or unload the FIFOs. The

registers form the bridge between the asynchronous interface, and the all logic that is synchronous to the system clock. They also allow the microprocessor to use

the upper bits of the address lines to select a particular time-slice in register space. The entire address bus, then, selects a particular register in a particular time-slice

or channel.

Divisor Latch

BAUD RATE

2304

50

1536

75

1047

110

857

134.5

768

150

384

300

192

600

96

1200

48

2400

32

3600

24

4800

16

7200

12

9600

6

19.2K

3

38.4K

2

57.6K

1

115.2K