Signal

Width

Direction

Description

a[m:0]

m+1

Input

Address Bus.

The Address input width is 8 for a 16-channel, 7 for an 8-channel, and 6 for a 4-channel imple-

mentation. The value of “m” is 7, 6, and 5 respectively.

Address bits [m-1:3] are used to select the port. Bits [2:0] are used to select the registers for a

given channel. Address bit m is reserved for future use and must be tied to logic low.

data_in[7:0]

8

Input

Data Bus input.

data_out[7:0]

8

Output

Data Bus output.

dout_enable

1

Output

Data Bus direction control signal. This signal is high, active, during the time data_out[7:0]

should be driven to the external data bus.

ads_n

1

Input

Address Strobe

When low, allows the value of a[7:0] and cs_n to propagate into the design. A low to high tran-

sistion latches the contents of a[7:0 and cs_n.

cs_n

1

Input

Chip Select.

When low, this signal indicates that the microprocessor has selected this device for an access

operation.

rd_n

1

Input

Read Strobe.

When rd transitions low, the contents of the register selected by A[2:0] on the channel selected

by A[6:3] will be driven on the data bus D[7:0].

wr_n

1

Input

Write Strobe.

When wr transitions from high to low, the levels of the data bus D[7:0] will be latched to the

register selected by A[2:0] on the channel selected by A[6:3].

intrq

1

Output

Interrupt Request.

This signal is high (active) when any channel has an interrupt available for the microprocessor.

An assertion on intrq indicates that the microprocessor should check the status registers on the

sourcing channel.

clk

1

Input

Synchronous clocking source.

This clock should be driven at a rate to insure reliable bit timing on the serial interfaces and at a

rate high enough to insure timely host interface A/C timing. A clock rate of of 29.4768 Mhz is the

recommend frequency.

reset_n

1

Input

Master Reset (async).

This low-active reset signal must conform to the setup time requirements specified in the data

sheet for the device used.

sin

num_channels

Input

Receive Data.

Receive Serial Data from the UART channel.

sout

num_channels

Output

Transmit Data.

Transmit Serial Data to the UART channel.

cts_n

num_channels

Input

Clear to Send.

When low, this signal indicates that the data set on the UART channel is ready to receive data.

Bit 4 of the MSR register reflects the condition of this line, while bit 0, when high, indicates a

change in the condition of this line.

dsr_n

num_channels

Input

Data Set Ready.

When low, this signal indicates that the data set is powered on. Bit 5 of the MSR register reflects

the condition of this line. Bit 1 of the MSR indicates a change in the condition of this signal when

high.

dcd_n

num_channels

Input

Data Carrier Detect.

When low, this signal indicates that the data set has detected a sinusoidal carrier on the channel

it is monitoring. Bit 7 of the MSR register reflects the condition of this line, while bit 3, when high,

indicates a change in the condition of this signal.

ri_n

num_channels

Input

Ring Indicator.

When low, this signal indicates that the Data Set (a modem) has detected ringing voltage from

the telephone line. Bit 6 of the MSR register reflects the condition of this line, while bit 2, when

high, indicates a change in the condition of this signal.

rts_n

num_channels

Output

Request to Send.

This signal, when driven low, indicates to the data set that the data terminal has data in the

transmit buffer that is ready for transmission. This signal can be asserted by setting bit 1 of the

MCR register.