Functional Description

The DDR SDRAM Controller core is partitioned into modules as shown in the block diagram and as described below.

CONTROLLER

The Controller module contains the main state machine, which controls the SDRAM accesses. The Controller is responsible for SDRAM bus arbitration, command

interpreting, bank-interleaving, and timing issues. The Controller instructs the ddr_interface module when to perform writes and reads from the DDR data bus.

DDR INTERFACE

The DDR Interface (ddr_interface) module is responsible for maintaining the bi-directional ddr_data bus, and for asserting all address and command signals to the

SDRAM. For a write operation, this module reads from the larger sys_data bus and, using the 2x clock and muxes, constructs the DDR data bus, writing out a new

value on every rising edge of the 2x clock which is strobed into the DDR SDRAM with ddr_dqs. For read operations, the opposite must occur. The Data Path reads in

the DDR data using sys_clk_fb rising edge as the time reference, and de-muxes the data into two separate 1x clock pipelines. These two 1x clock pipelines are then

concatenated to form the larger sys_data bus, which is provided to the user.

CLOCK MODULE

The Clock module (clk_module) instantiates all of the PLLs and global clocks required for the DDR Core. One PLL creates a 1x de-skewed clock that is fed to most of

the logic in the core, plus it also creates a 2x clock which generates the 2X DDR related clocks used for write-related operations. The other PLL generates a delayed

clock that is used in the read-related operations.

Figure 1: MC-ACT-SDRAMDDR Logic Symbol

Family

Device

Utilization

Performance

COMB

SEQ

Total

Axcelerator

AX250-2

20%

40%

27%

100 MHz

Table 1: Device Utilization and Performance

reset

sys_clk

sys_addr

sys_data_i

sys_cmd

sys_data_m

sys_data_valid

ctlr_ready

read_en

ddr_clk

ddr_clkb

ddr_addr

ddr_dm

ddr_bank

ddr_ras

sys_data_o

ddr_cas

ddr_we

ddr_dqs

ddr_cs

ddr_cke

ddr_dq

sys_cmd_ack

ddr_clk_fb

fpga_clk

smp_delay