Timing

All timing diagrams assume that all banks were previously closed, and that BURST-4 accesses were issued. All timing is based on a 100 MHz sys_clk.

Figure 3: Read Command

Figure 4: Write Command

0ns

20ns

40ns

60ns

80ns

100ns

120ns

140ns

sys_clk[0]

sys_cmd[0]

sys_addr[0]

sys_cmd_ack[0]

ctlr_ready[0]

sys_data_i[0]

sys_data_m[0]

read_en[0]

sys_data_o[0]

sys_data_valid[0]

nop

read

nop

Address

Data 0 Data 1

0ns

20ns

40ns

60ns

80ns

100ns

120ns

140ns

160ns

sys_clk[0]

sys_cmd[0]

sys_addr[0]

sys_cmd_ack[0]

ctlr_ready[0]

read_en[0]

sys_data_i[0]

sys_data_m[0]

sys_data_o[0]

sys_data_valid[0]

nop

write

nop

Address

Data 0 Data 1