Verification and Compliance

Functional and timing simulation has been performed on the DDR SDRAM Controller using VHDL Test Benches. Simulation vectors used for verification are provided

with the core.

Signal Descriptions

The following signal descriptions define the IO signals.

Signal

Direction

Width

Description

Global Signals

SYS_CLK

Input

1

System clock

DDR_CLK_FB

Input

1

ddr_clk from DDR SDRAM

FPGA_CLK

Output

1

primary H-CLOCK clock used by core and available for host

interface

RESET

Input

1

Active high system reset

Interface to System

SYS_DATA_I

Input

SYS_DATA_BITS System write data

SYS_DATA_M

Input

SYS_MASK_BITS System write data mask

SYS_ADDR

Input

SYS_ADDR_BITS System address

SYS_CMD

Input

7

DDR command bus

SYS_DATA_O

Output

SYS_DATA_BITS System read data

SYS_DATA_VALID

Output

1

High when sys_data_o is valid

SYS_CMD_ACK

Output

1

High when command is accepted

CTLR_READY

Output

1

High when controller can accept a cmd

READ_EN

Output

1

When high, controller needs new data in 2 clocks

Interface to DDR SDRAM

DDR_ADDR

Output

DDR_ADDR_BITS DDR SDRAM address bus

DDR_DQ

Output

DDR_DATA_BITS DDR SDRAM data bus

DDR_DQS

Input/Output

8

DDR SDRAM data strobe

DDR_RAS

Input/Output

1

DDR SDRAM row address strobe

DDR_CAS

Output

1

DDR SDRAM column address strobe

DDR_WE

Output

1

DDR SDRAM write enable

DDR_BANK

Output

DDR_BANK_BITS DDR SDRAM bank bus

DDR_CLK

Output

1

DDR SDRAM clock

DDR_CLKB

Output

1

DDR SDRAM inverted clock

DDR_CS

Output

1

DDR SDRAM chip select

DDR_CKE

Output

1

DDR SDRAM clock enable

DDR_DM

Output

DDR_MASK_BITS DDR SDRAM data mask bus

Table 2: Core I/O Signals