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LTC1702A

1702afa

cycles. Over just a few cycles, however, the external

components conspire to limit the speed that the output

can move. Consider our typical 5V to 1.6V circuit, sub-

jected to a 1A to 5A load transient. Initially, the loop is in

regulation and the DC current in the output capacitor is

zero. Suddenly, an extra 4A start flowing out of the output

capacitor while the inductor is still supplying only 1A. This

sudden change will generate a (4A)(CESR)voltage step at

the output; with a typical 0.015

Ω output capacitor ESR,

this is a 60mV step at the output, or 3.8% (for a 1.6V output

voltage).

Very quickly, the feedback loop will realize that something

has changed and will move at the bandwidth allowed by

the external compensation network towards a new duty

cycle. If the bandwidth is set to 50kHz, the COMP pin will

get to 60% of the way to 90% duty cycle in 3

µs. Now the

inductor is seeing 3.5V across itself for a large portion of

the cycle, and its current will increase from 1A at a rate set

by di/dt = V/L. If the inductor value is 0.5

µH, the di/dt will

be 3.5V/0.5

µH or 7A/µs. Sometime in the next few micro-

seconds after the switch cycle begins, the inductor current

will have risen to the 5A level of the load current and the

output capacitor will stop losing charge.

Note that the output voltage will stop dropping before the

inductor current reaches this new output current level.

Recall that any practical output capacitor looks like a pure

capacitance in series with some amount of ESR. When a

load transient hits, virtually all of the initial voltage drop at

the output is due to IR drop across the ESR. The output

capacitance begins to discharge at the same time and

continues until the inductor current rises to match the new

output current level.

The output voltage, however, will turn around and start

heading the right way before this happens. The next time

the top MOSFET turns on, the inductor current will begin

increasing linearly. This increasing current flows almost

entirely into the capacitor, going through the ESR as it

does so (Figure 16). Positive di/dt in the inductor causes

positive dv/dt in the ESR, regardless of what the “pure”

capacitance is doing. The output voltage will turn around

when the positive dv/dt across the ESR exceeds the

negative dv/dt across the pure capacitance. If the expected

load step (

∆I) is known, an optimum inductor value can be

chosen:

ESR

OUT

≤

()

∆

–• •

APPLICATIONS INFORMATION

–

VOUT

IOUT

1702A F16a

VESR

COUT

VCAP

VSW

VCAP

VOUT

TRANSIENT

HITS

VOUT

TURNS

AROUND

IL > IOUT

TIME

VESR

IOUT

VOUT

VESR

IOUT

VCAP

VOUT(NOMINAL)

1702A F16b

Figure 16b. Transient Recovery Curves

Figure 16a. Capacitor Parasitics

Affecting Transient Recovery

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