LTC4306

4306f

16

Assume in Figure 5 that the total parasitic bus capacitance

on SDA1 due to trace and device capacitance is 100pF. To

ensure that the boost currents are active during rising

edges, the pull-up resistor must be strong enough to

cause the SDA1 pin voltage to rise at a rate of 0.8V/

µs as

the pin voltage is rising above 0.8V. The equation is:

Rk

VV

ns

V

PULL UP MAX

BUSMIN

−

Ω

⎡

⎣⎢

,

(– .

) •

0 8

1250

⎤⎤

⎦⎥

⎧

⎨

⎩

⎫

⎬

⎭

[]

CpF

BUS

(1)

up resistor smaller (i.e., stronger pull-up) than 27.1k, so

a 10k resistor works fine.

ALERT, READY and GPIO Component Selection

The pull-up resistors on the ALERT and READY pins must

provide a maximum pull-up current of 3mA, so that the

LTC4306 is capable of holding the pin at logic low voltages

below 0.4V. When choosing LEDs to be driven by the

LTC4306’s GPIO pins, make sure that the required LED

sinking current is less than 5mA, and add a current-

limiting resistor in series with the LED.

Level Shifting Considerations

voltage is less than or equal to both of the downstream bus

pull-up voltages, so buses 1 and 4 can be active at the

same time. Likewise, the rise time accelerators can be

turned on for the downstream buses, but must never be

activated on SCLIN and SDAIN, because doing so would

rising edges.

Other Application Circuits

Figure 6 illustrates how the LTC4306 can be used to

expand the number of devices in a system by using nested

addressing. Each I/O card contains a temperature sensor

having device address 1001 000. If the four I/O cards were

plugged directly into the backplane, the four sensors

would require four unique addresses. However, if masters

use the LTC4306 in multiplexer mode, where only one

downstream channel is connected at a time, then each

I/O card can have a device with address 1001 000 and no

problems will occur.

Figures 7 and 8 show two different methods for hot-

swapping I/O cards onto a live two-wire bus using the

LTC4306. The circuitry of Figure 7 consists of an LTC4306

residing on the edge of an I/O card having four separate

downstream buses. Connect a 200k resistor to ground

from the ENABLE pin and make the ENABLE pin the

shortest pin on the connector, so that the ENABLE pin

remains at a constant logic low while all other pins are

connecting. This ensures that the LTC4306 remains in its

default high impedance state and ignores connection

transients on its SDAIN and SCLIN pins until they have

established solid contact with the backplane 2-wire bus. In

addition, make sure that the ALERT connector pin is

contact with the I/O card pull-up supply pin and powers

the pull-up resistors on ALERT1–ALERT4 before ALERT

makes contact.

Figure 8 illustrates an alternate SDA and SCL hot-swap-

ping technique, where the LTC4306 is located on the

backplane and an I/O card plugs into downstream channel

4. Before plugging and unplugging the I/O card, make sure

that channel 4’s downstream switch is open, so that it does

not disturb any 2-wire transaction that may be occurring

at the moment of connection/disconnection. Note that

pull-up resistor, R17, on ALERT4 should be located on the

backplane and not the I/O card to ensure proper operation

of the LTC4306 when the I/O card is not present. The pull-

up resistors on SCL4 and SDA4, R15 and R16 respec-

tively, may be located on the I/O card, provided that

downstream bus 4 is never activated when the I/O card is

not present. Otherwise, locate R15 and R16 on the

backplane.

APPLICATIO S I FOR ATIO