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LTC2926IGN 数据表(PDF) 13 Page - Linear Technology |
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LTC2926IGN 数据表(HTML) 13 Page - Linear Technology |
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13 / 28 page  LTC2926 13 2926fa Figure 7. Typical Application with Master Supply RTB1 RTA1 2926 F07 LTC2926 S1 FB1 OUT IN SENSE RAMPBUF TRACK1 TRACK2 GND PGTMR VIN RTB2 RTA2 FAULT 10k 0.1 µF CPGTMR CMGATE MGATE 10 Ω RSGATE RAMP RX0 VIN STATUS STATUS/PGI ON ON/OFF 10k 3.3V MODULE VIN Q0 Q3 SGATE2 10 Ω Q2 SGATE1 10 Ω MASTER D1 RFB1 RFA1 S2 FB2 D2 RFB2 RFA2 FAULT VCC VIN OUT IN SENSE RX1 1.8V MODULE VIN Q1 1.8V SLAVE1 OUT IN SENSE RX2 2.5V MODULE VIN 2.5V SLAVE2 Figure 8. Typical Application Without Master Supply Ramp Buffer The RAMPBUF pin provides a buffered version of the RAMP pin voltage that drives the resistive dividers on the TRACK pins. When there is no external MOSFET, it sources or sinks up to 3mA to drive the track resistors even though the MGATE pin only supplies 10µA (Figure 8). The RAMPBUF pin also proves useful in systems with an external MOSFET. If RTBn were directly connected to the MOSFET’s source (the master output), the servo mechanism of the tracking cell could potentially drive the master output towards 0.8V when the MOSFET is off. The ramp buffer prevents this by eliminating that path for current. Fault Input/Output The FAULT pin allows external upstream monitoring circuits to control and to communicate with the LTC2926. The pin is driven internally by an N-channel MOSFET pull-down to GND, and by an 8.5µA pull-up to VCC through a series diode. Under normal conditions, the MOSFET is off and the current pulls the FAULT pin voltage high. When an upstream monitor signal pulls FAULT below 0.5V, the LTC2926’s internal fault latch is set, which immediately opens the remote sense switches and cuts off the master and slave supplies by pulling MGATE, SGATE1 and SGATE2 to GND. A fault also activates the internal MOSFET pull-down on the STATUS/PGI pin, which indicates to external downstream monitoring circuits that the supplies are no longer valid (see Status Output). Until the fault latch is reset, the sup- plies stay disconnected and an internal pull-down keeps the FAULT pin low as a signal to upstream monitors. Fault latch reset is initiated by bringing the ON pin voltage below 0.5V, and completed when PGTMR is <0.1V. Reduc- ing the VCC pin voltage below VCC(UVLO) – ΔVCC(UVLO), typically 2.35V, also resets the fault latch. After it is cleared, the fault latch is armed by bringing the ON pin voltage above 0.6V. No faults can be latched until after the latch is armed. The FAULT pin is pulled up by 8.5µA to VCC through a Schottky diode, which allows the pin to be pulled safely above the LTC2926’s supply if required. Leave the FAULT pin unconnected if it is unused. APPLICATIO S I FOR ATIO RTB1 RTA1 2926 F08 LTC2926 S1 FB1 RAMPBUF TRACK1 TRACK2 GND PGTMR VIN RTB2 RTA2 FAULT 10k 0.1 µF CPGTMR CMGATE MGATE RSGATE RAMP VIN STATUS STATUS/PGI ON ON/OFF 10k SGATE2 10 Ω Q2 NC SGATE1 10 Ω D1 RFB1 RFA1 S2 FB2 D2 RFB2 RFA2 FAULT VCC VIN OUT IN SENSE RX1 1.8V MODULE VIN Q1 1.8V SLAVE1 OUT IN SENSE RX2 2.5V MODULE VIN 2.5V SLAVE2 |
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