Watchdog Timer and ST Input

A watchdog timer stops and restarts a microprocessor that is

“hung-up”. Through the time delay input, TD, three watchdog

time-out periods are selectable: 150ms, 610ms and 1,200ms. If the

strobe input, ST, is not strobed LOW prior to timeout, reset signals

become active. On power-up or after the supply voltage returns to

an in-tolerance condition, the reset signal remains active for

250ms minimum, allowing the power supply and system micro-

processor to stabilize.

ST Pulses as short as 20ns can be detected.

Figure 5. Timing Diagram: Strobe Input

RESET

ST

Valid

Strobe

Valid

Strobe

Invalid

Strobe

Note: ST is ignored whenever a reset is active.

(Min)

(Max)

1832_08.eps

©

1999 IMP, Inc.

408-432-9100/www.impweb.com

5

IMP1

832

Application Information

Figure 6. Application Circuit: Watchdog Timer

A HIGH-to-LOW ST signal transition must be regularly issued

no later than the minimum time-out period defined by the state of

the TD signal. This guarantees the watchdog timer does not

time-out.

Timeouts periods of approximately 150ms, 610ms or 1,200ms are

selected through the TD pin.

1832_06.eps

PBRST

Supply

Voltage

1

TD

2

ST

TOL

IMP1832

mP

Decoder

3

4

RESET

GND

8

7

6

5

RESET

MREQ

Address

Bus

RESET

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5

10

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The watchdog timer can not be disabled. It must be strobed with

a high-to-low transition to avoid a watchdog timeout and reset.