IMP1832 datasheet(4/7 Pages) A1PROS

4 / 7 page

On power-down, once VCC falls below the reset threshold RESET

stays LOW and is guaranteed to be 0.4V or less until VCC drops

below 1.2V. The active HIGH reset signal is valid down to a VCC

level of 1.2V also.

Manual Reset Operation

Push-button switch input, PBRST, allows the user to override the

internal trip point detection circuits and issue reset signals. The

pushbutton input is debounced and is pulled HIGH through an

internal 40k

Ω resistor.

When PBRST is held LOW for the minimum time tPB , both resets

become active and remain active for a minimum time period of

250ms after PBRST returns HIGH.

The debounced input is guaranteed to recognize pulses greater

than 20ms. No external pull-up resistor is required, since PBRST

is pulled HIGH by an internal 40k

Ω resistor.

The PBRST can be driven from a TTL or CMOS logic line or short-

ed to ground with a mechanical switch.

)

(

408-432-9100/www.impweb.com

1999 IMP, Inc.

IMP1

IMP1832

832

Application Information

Supply Voltage Monitor

The IMP1832 monitors the microprocessor or microcontroller

power supply and issues reset signals, both active HIGH and

active LOW, that halt processor operation whenever the power

supply voltage levels are outside a predetermined tolerance.

Tolerance levels are set with the TOL pin.

RESET and RESET signals are generated at the last moment of a

valid VCC signal. On power-up, both reset signals are active for a

minimum of 250ms after the supply has returned to intolerance

level. This allows the power supply and monitored processor to

stabilize before instruction execution is allowed to begin.

Trip Point Tolerance Selection

With TOL connected to VCC, RESET and RESET become active

whenever VCC falls below 2.64V. RESET and RESET become active

when VCC falls below 2.98V if TOL is connected to ground.

After VCC has risen above the trip point set by TOL, RESET and

RESET remain active for a minimum time period of 250ms.

Figure 1. Timing Diagram: Power Up

Figure 2. Timing Diagram: Power Down

1832_04.eps

VCCTP(MAX)

VCCTP

VCCTP(MIN)

VCC

RESET

tRPU

VOH

VOL

Figure 3. Timing Diagram: Pushbutton Reset

VIH

VIL

VOH

VOL

RESET

PBRST

tPDLY

tPB

tRST

1832_07.eps

Figure 4. Application Circuit: Pushbutton Reset

1832_05.eps

PBRST

Supply

Voltage

VCC

TOL

IMP1832

µP

RESET

GND

RESET

VCCTP(MAX)

VCCTP

VCCTP(MIN)

VCC

RESET

VOH

VOL

tRPD

1832_03.eps

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