TL052IP datasheet(6/65 Pages) TI

6 / 65 page

TL05x, TL05xA, TL05xY

ENHANCED-JFET LOW-OFFSET

OPERATIONAL AMPLIFIERS

SLOS178 – FEBRUARY 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

TL054 chip information

This chip, when properly assembled, displays characteristics similar to the TL054C. Thermal compression or

ultrasonic bonding may be used on the doped-aluminum bonding pads. These chips may be mounted with

conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

–

1OUT

1IN +

1IN –

VCC+

(4)

(6)

(3)

(2)

(5)

(1)

–

(7)

2IN +

2IN –

2OUT

(11)

VCC –

–

3OUT

3IN +

3IN –

(13)

(10)

(9)

(12)

(8)

–

(14)

4OUT

4IN +

4IN –

(6)

(7)

(8)

(9)

122

CHIP THICKNESS: 15 MILS TYPICAL

BONDING PADS: 4

× 4 MILS MINIMUM

TJmax = 150°C

TOLERANCES ARE

±10%.

ALL DIMENSIONS ARE IN MILS.

PIN (11) IS INTERNALLY CONNECTED

TO BACKSIDE OF THE CHIP.

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)

TL052IP 数据表(PDF) 6 Page - Texas Instruments

TL052IP 数据表(HTML) 6 Page - Texas Instruments

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