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TL052IP 数据表(PDF) 63 Page - Texas Instruments

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部件名 TL052IP
功能描述  ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
PDF  65 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TL052IP 数据表(HTML) 63 Page - Texas Instruments

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TL05x, TL05xA, TL05xY
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178 – FEBRUARY 1997
63
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim
Parts
™, the model generation software used
with Microsim
PSpice
™. The Boyle macromodel (see Note 5) and subcircuit Figure 92 are generated using the
TL05x typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations
of the following key parameters can be generated to a tolerance of 20% (in most cases):
D Maximum positive output voltage swing
D Maximum negative output voltage swing
D Slew rate
D Quiescent power dissipation
D Input bias current
D Open-loop voltage amplification
D Unity-gain frequency
D Common-mode rejection ratio
D Phase margin
D DC output resistance
D AC output resistance
D Short-circuit output current limit
NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers”,
IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
OUT
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
.SUBCKT TL05x 1 2 3 4 5
C1
11
12
3.988E–12
C2
6
7
15.00E–12
DC
5
53
DX
DE
54
5
DX
DLP
90
91
DX
DLN
92
90
DX
DP
43DX
EGND
99
0
POLY (2) (3,0) (4,0) 0 .5 .5
FB
7
99
POLY (5) VB VC VE VLP
+ VLN 0 2.875E6 –3E6 3E6 3E6 –3E6
GA
6
0
11
12 292.2E–6
GCM
0
6
10
99 6.542E–9
ISS
3
10
DC 300.0E–6
HLIM
90
0
VLIM 1K
J1
11
2
10 JX
J2
12
1
10 JX
R2
6
9
100.0E3
RD1
4
11
3.422E3
RD2
4
12
3.422E3
R01
8
5
125
R02
7
99
125
RP
3
4
11.11E3
RSS
10
99
666.7E6
VB
9
0
DC 0
VC
3
53
DC 3
VE
54
4
DC 3.7
VLIM
7
8
DC 0
VLP
91
0
DC 28
VLN
0
92
DC 28
.MODEL DX D (IS=800.0E–18)
.MODEL JX PJF (IS=15.00E–12 BETA=185.2E–6
+ VTO= –.1)
.ENDS
VCC +
RP
IN –
2
IN +
3
VCC –
VAD
RD1
11
J1
J2
10
RSS
ISS
3
12
RD2
60
VE
54
DE
DP
VC
DC
4
C1
53
R2
6
9
EGND
VB
FB
C2
GCM
GA
VLIM
8
5
RO1
RO2
HLIM
90
DLP
91
DLN
92
VLN
VLP
99
7
Figure 92. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
Macromodels, simulation models, or other models provided by TI,
directly or indirectly, are not warranted by TI as fully representing all
of the specification and operating characteristics of the
semiconductor product to which the model relates.



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