TMS320UC5409 datasheet(21/74 Pages) TI

21 / 74 page

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

sample rate generator external clock options (continued)

Table 5. Pin Control Register (PCR) Bit Field Description

BIT

NAME

FUNCTION

15 – 14

Reserved

Reserved. Pins are not used.

XIOEN

Transmit/Receive general-purpose I/O mode ONLY when XRST=0 in the SPCR(1/2)

XIOEN = 0

DX pin is not a general-purpose output. FSX and CLKX are not general-purpose I/Os.

XIOEN = 1

DX pin is a general-purpose output. FSX and CLKX are general-purpose I/Os. These

serial port pins do not perform serial port operations.

RIOEN

Transmit/Receive general-purpose I/O mode ONLY when RRST=0 in the SPCR(1/2)

RIOEN = 0

DR and CLKS pins are not general-purpose inputs. FSR and CLKR are not

general-purpose I/Os.

RIOEN = 1

DR and CLKS pins are general-purpose inputs. FSR and CLKR are general-purpose

I/Os. These serial port pins do not perform serial port operations. The CLKS pin is

affected by a combination of RRST and RIOEN signals of the receiver.

FSXM

Transmit frame synchronization mode

FSRM = 0

Frame synchronization signal derived from an external source.

FSRM = 1

Frame synchronization is determined by the sample rate generator frame

synchronization mode bit (FSGM) in the SRGR2.

FSRM

Receive frame synchronization mode

FSRM = 0

Frame synchronization pulses generated by an external device. FSR is an input pin.

FSRM = 1

Frame synchronization generated internally by the sample rate generator. FSR is an

output pin except when GSYNC=1 in the SRGR.

CLKRM

Receiver clock mode

Case 1: Digital loop-back mode is not set (CLB=0) in SPCR1.

CLKRM = 0

Receive clock (CLKR) is an input pin driven by an external clock.

CLKRM= 1

CLKR is an output pin and is driven by the internal sample rate generator

Case 2: Digital loop-back mode set (CLB=1) in SPCR1

CLKRM = 0

Receive clock (

Not the CLKR pin) is driven by transmit clock (CLKX), which is based

on CLKXM bit in the PCR. CLKR pin is in high-impedance mode.

CLKRM= 1

CLKR is an output pin and is driven by the transmit clock. The transmit clock is derived

based on the CLKXM bit in the PCR.

CLKXM

Transmitter clock mode

CLKXM = 0

Receiver/transmitter clock is driven by an external clock with CLK(R/X) as an input

CLKXM= 1

CLK(R/X) is an output pin and is driven by the internal sample rate generator

During SPI mode (CLKSTP is a non-zero value):

CLKXM = 0

McBSP is a slave and clock (CLKX) is driven by the SPI master in the system. CLKR

is internally driven by CLKX.

CLKXM= 1

McBSP is a master and generates the clock (CLKX) to drive its receive clock (CLKR)

and the shift clock of the SPI-compliant slaves in the system.

TMS320UC5409 数据表(PDF) 21 Page - Texas Instruments

TMS320UC5409 数据表(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

数据表下载