TMS320UC5409 datasheet(23/74 Pages) TI

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TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

sample rate generator external clock options (continued)

Table 7. Sample Rate Generator Register 2 (SRGR2) Bit Field Descriptions

BIT

NAME

FUNCTION

GSYNC

Sample rate gnereator clock synchronization. Only used when the external clock (CLKS) drives the

sample rate generator clock (CLKSM=0)

GSYNC = 0

The sample rate generator clock (CLKG) is free-running.

GSYNC = 1

The sample rate generator clock (CLKG) is running. But CLKG is resynchronized and

frame sync signal (FSG) is generated only after detecting the receive frame

synchronization signal (FSR). Also, frame period (FPER) is a don’t care because the

period is dictated by the external frame sync pulse.

CLKSP

CLKS polarity clock edge select. Only used when the external clock (CLKS) drives the sample rate

generator clock (CLKSM=0).

CLKSP = 0

Rising edge of CLKS generates CLKG and FSG.

CLKSP = 1

Falling edge of CLKS generates CLKG and FSG.

CLKSM

McBSP sample rate generator clock mode

SCLKME = 0

CLKSM = 0

Sample rate generator clock derived from the CLKS pin

(in PCR)

CLKSM = 1

Sample rate generator clock derived from CPU clock

SCLKME = 1

CLKSM = 0

Sample rate generator clock derived from CLKR pin

(in PCR)

CLKSM = 1

Smaple rate generator clock derived from CLKX pin

FSGM

Sample rate generator transmit frame synchronization mode. Used when FSXM=1 in the PCR.

FSGM = 0

Transmit frame sync signal (FSX) due to DXR(1/2) copy

FSGN = 1

Transmit frame sync signal driven by the sample rate generator frame sync signal

(FSG)

11 – 0

FPER

Frame period. This determines when the next frame sycn signal should become active. Range: up to

212; 1 to 4096 CLKG periods.

hardware timer

The ’UC5409 device features one 16-bit timing circuit with a 4-bit prescaler. The main counter of each timer is

decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is

generated. The timer can be stopped, restarted, reset, or disabled by specific control bits.

clock generator

The clock generator provides clocks to the ’UC5409 device, and consists of an internal oscillator and a

phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided

by using a crystal resonator with the internal oscillator, or from an external clock source. The reference clock

input is then divided by two (DIV mode) to generate clocks for the ’UC5409 device, or the PLL circuit can be

used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor,

allowing use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive circuit that,

once synchronized, locks onto and tracks an input clock signal.

When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input

signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,

other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the

’UC5409 device.

TMS320UC5409 数据表(PDF) 23 Page - Texas Instruments

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