TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

16

POST OFFICE BOX 655303

Start Delimiter

Operation Code

PHY Address

Register Address

Turnaround

Data

01

10

AAAAA

RRRRR

Z0

DDDD.DDDD.DDDD.DDDD

Figure 4. MII Frame Format: Reads

Start Delimiter

Operation Code

PHY Address

Register Address

Turnaround

Data

01

01

AAAAA

RRRRR

10

DDDD.DDDD.DDDD.DDDD

Figure 5. MII Frame Format: Writes

start delimiter

The start of a frame is indicated by a 01 pattern. This pattern ensures transitions from the default logic 1 line

state to 0 and back to 1.

operation code

The operation code for a read is 10, while the code for a write is 01.

PHY address

The PHY address is five bits wide, which allows 32 unique PHY addresses. The first PHY address bit transmitted

and received is the most-significant bit (MSB) of the address. The two least-significant bits (LSBs) represent

the PHY number within the package. The upper three bits for each internal PHY are read from the DEVSEL pins.

register address

The register address is five bits wide, allowing 32 individual registers to be addressed within each PHY. Refer

to the address maps (Figures 4 and 5) for the addresses of individual registers.

turn around

An idle-bit time, during which no device actively drives the MDIO signal, must be inserted between the register

address field and the data field of a read frame, to avoid contention. During a read frame, the PHY drives a

0 bit onto MDIO for the bit time following the idle bit and preceding the data field. During a write frame, this field

must consist of a 1 bit followed by a 0 bit.

data

The data field is composed of 16 bits. The first data bit transmitted and received is the MSB of the data payload.