TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

17

POST OFFICE BOX 655303

PHY generic control register – GEN_ctl at 0x0

BYTE 1

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

BYTE 0

0

R

E

S

E

T

L

O

O

P

B

A

C

K

0

A

N

E

N

A

B

L

E

P

D

O

W

N

I

S

O

L

A

T

E

A

N

R

E

S

T

A

R

T

D

U

P

L

E

X

C

O

L

T

E

S

T

RESERVED

Figure 6. PHY Generic Control Register

Table 3. PHY Generic Control Register Bit Functions

BIT

FUNCTION

DIRECTION†

DEFAULT

NO.

NAME

FUNCTION

DIRECTION†

DEFAULT

15

RESET‡

Reset a PHY. Writing a 1 RESET resets the whole device, and all registers revert to

their default values. RESET is self clearing. It is always read as 0. It is not possible

to reset one PHY separately from the others. Operation of the device is not ensured

for a duration of 50 ms after a software reset.

R/W

0

14

LOOPBACK

Internal loopback mode. LOOPBACK enables the internal loopback within the

individual PHY. When LOOPBACK is set to 1, data is wrapped internally within the

PHY and does not appear on the network. Collision detection is disabled, and data

transmitted appears at the receive pins. While in loopback mode, the device pins are

placed in noncontentious states.

R/W

Pin

13

Reserved

RO

0

12

ANENABLE

Auto-negotiation enable. When set, ANENABLE allows auto-negotiation to take

place.

R/W

Pin

11

PDOWN

Power-down mode. When set, PDOWN places the PHY in a power-down mode. In

this mode, it is not possible to receive or transmit data, although it is possible to

continue to process management-data frames. IEEE Std 802.3 states that the PHY

must be allowed 500 ms of initialization time after it is taken out of power-down state

before data transmission and reception can be started. See Note 1.

R/W

0

10

ISOLATE

PHY pin isolation. When set, the PHY electrically isolates itself from the pins. In the

ISOLATE state, the PHY does not respond to TXD or TXEN but presents a high

impedance on RXD, RXCLK, and COL. However, it still responds to MII data frames.

R/W

0

9

ANRESTART

Auto-negotiation restart. Setting ANRST causes auto-negotiation to be restarted.

R/W

0

8

DUPLEX

Full-duplex mode select. Setting DUPLEX forces this PHY into full-duplex mode.

Resetting it forces half-duplex. For DUPLEX to have any effect, the DUPLEX pin on

the package must not be driven externally.

R/W

Pin

7

COLTEST

Collision-test enable. Setting COLTEST causes this PHY to assert COL when TXEN

is asserted.

R/W

0

6–0

RESERVED

Reserved

0

† RO = read only, R/W = read/write

‡ This bit is set for the TNETE2004, not for each PHY.

NOTE 1: If all four PHYs are in power-down mode simultaneously, then reset must be used to power up the device. It is not possible to power

up an individual PHY if all four PHYs are in power-down mode.